Oscillation circuit and semiconductor integrated circuit including the same

ABSTRACT

An oscillation circuit including, a latch for generating an output signal based on a first signal and a second signal, an electric-charge charge/discharge unit which has first and second capacitors, and charges or discharges the first and second capacitors complementarily based on the output signal, a first comparator which compares a first voltage according to electric charge accumulated in the first capacitor and a first reference voltage, and outputs the first signal, a second comparator which compares a second voltage according to electric charge accumulated in the second capacitor and the first reference voltage, and outputs the second signal, and a control unit for controlling a timing, to compensate for variations of signals in the latch, the first comparator, and the second comparator, at which respective voltage levels of the first reference voltage and the first voltage match.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a Continuation application of U.S. patentapplication Ser. No. 13/525,099, filed on Jun. 15, 2012, which is basedon Japanese Patent Application No. 2011-175732 filed on Aug. 11, 2011,the entire contents of which are hereby incorporated by reference.

BACKGROUND

The present invention relates to an oscillation circuit and asemiconductor integrated circuit including the same, and in particular,relates to an oscillation circuit for outputting an oscillation signalhaving an accurate frequency and a semiconductor integrated circuitincluding the same.

In recent years, oscillation circuits for outputting oscillation signalshaving accurate frequencies have been required. Related techniques aredisclosed in Japanese Unexamined Patent Publication No. 2007-243922(Patent Document 1) and Japanese Unexamined Patent Publication No.2006-86997 (Patent Document 2).

An oscillation circuit disclosed in Patent Document 1 includes first andsecond capacitors, first and second comparison circuits, an RS flip-flopcircuit, and first and second charge/discharge control circuits.

The first and second capacitors are charged or discharged by currentgenerated by a constant current source. The first comparison circuitcompares a first voltage V1 according to the amount of electric chargestored in the first capacitor and a first reference voltage Vst, andoutputs a first signal indicating that the first voltage V1 has reachedthe first reference voltage Vst. The second comparison circuit comparesa second voltage V2 according to the amount of electric charge stored inthe second capacitor and a second reference voltage Vst, and outputs asecond signal indicating that the second voltage V2 has reached thesecond reference voltage Vst.

The RS flip-flop circuit is set by one of the first signal and thesecond signal, and reset by the other. The first charge/dischargecontrol circuit charges the first capacitor when the RS flip-flopcircuit is set, and discharges the first capacitor when the RS flip-flopcircuit is reset. The second charge/discharge control circuit chargesthe second capacitor when the RS flip-flop circuit is reset, anddischarges the second capacitor when the RS flip-flop circuit is set.

Thereby, according to the description in Patent Document 1, theoscillation circuit outputs an oscillation signal having a stablefrequency even when noise occurs.

An oscillation circuit disclosed in Patent Document 2 includes anoscillator, a frequency-voltage converter, a difference detector, and anintegrator, which are coupled in a closed loop. The oscillator generatesan output signal which oscillates at a frequency according to a controlsignal. The frequency-voltage converter generates a detection signalhaving a voltage according to the frequency of the output signal. Thedifference detector generates, a difference signal indicating thedifference between the detection signal and a reference signal. Theintegrator generates a control signal by integrating the differencesignal.

Further, the oscillator has a relaxation signal generation circuit forgenerating a relaxation control signal by relaxing a change in thecontrol signal and an output signal generation circuit for generating anoutput signal which oscillates at a frequency according to therelaxation control signal.

Thereby, according to the description in Patent Document 2, theoscillation circuit generates a high-frequency output signal at lowpower consumption with stability and accuracy. Further, to suppress anincrease in power consumption and a reduction in frequency accuracy, theoscillation circuit is configured without a comparator.

SUMMARY

In the oscillation circuit disclosed in Patent Document 1, ideally theoutput signal of the RS flip-flop circuit changes from an L level to anH level or changes from the H level to the L level (the logic valuethereof changes) at the moment when the first voltage V1 reaches thereference voltage Vst or the second voltage V2 reaches the referencevoltage Vst. However, in reality, the logic value of the output signal(oscillation signal) of the RS flip-flop circuit changes after a delaytime Td caused by the operation delay of the first and second comparisoncircuits and the RS flip-flop circuit has elapsed from the time when thefirst voltage V1 reaches the reference voltage Vst or the time when thesecond voltage V2 reaches the reference voltage Vst.

Therefore, in the oscillation circuit of the related technique, there isa problem that the frequency of the oscillation signal varies as thedelay time Td varies with fluctuations in temperature or power supplyvoltage. That is, there is a problem that the oscillation circuit of therelated technique cannot output an oscillation signal having an accuratefrequency.

According to one aspect of the present invention, an oscillation circuitincludes an RS flip-flop for generating an output signal (oscillationsignal) based on a set signal and a reset signal, an electric-chargecharge/discharge unit which has first and second capacitors and chargesor discharges the first and second capacitors complementarily based onthe output signal, a first comparator which compares a first voltageaccording to electric charge accumulated in the first capacitor and afirst reference voltage and outputs the set signal, a second comparatorwhich compares a second voltage according to electric charge accumulatedin the second capacitor and the first reference voltage and outputs thereset signal, and a control unit for controlling a timing at whichrespective voltage levels of the first reference voltage and the firstvoltage match and a timing at which respective voltage levels of thefirst reference voltage and the second voltage match in accordance witha frequency of the output signal.

With the above circuit configuration, the oscillation circuit can outputan oscillation signal having an accurate frequency.

According to aspects of the invention, it is possible to provide theoscillation circuit that can output an oscillation signal having anaccurate frequency.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the configuration of an oscillationcircuit according to a first embodiment of the invention;

FIG. 2 is a timing chart showing the operation of the oscillationcircuit according to the first embodiment of the invention;

FIG. 3 is a block diagram showing the configuration of an oscillationcircuit according to a second embodiment of the invention;

FIG. 4 is a timing chart showing the operation of the oscillationcircuit according to the second embodiment of the invention;

FIG. 5 is a block diagram showing the configuration of an oscillationcircuit according to a third embodiment of the invention;

FIG. 6 is a timing chart showing the operation of the oscillationcircuit according to the third embodiment of the invention;

FIG. 7 is a block diagram showing the configuration of an oscillationcircuit according to a fourth embodiment of the invention;

FIG. 8 is a block diagram showing the configuration of an oscillationcircuit according to a fifth embodiment of the invention;

FIG. 9 is a block diagram showing the configuration of an oscillationcircuit according to a sixth embodiment of the invention;

FIG. 10 is a diagram for explaining a control signal supplied to areference voltage generation unit according to the sixth embodiment ofthe invention;

FIG. 11 is a block diagram showing the configuration of an oscillationcircuit according to a seventh embodiment of the invention;

FIG. 12 is a diagram for explaining control signals supplied to areference voltage generation unit according to the seventh embodiment ofthe invention;

FIG. 13 is a block diagram showing the configuration of an oscillationcircuit according to an eighth embodiment of the invention;

FIG. 14 is a timing chart showing the operation of the oscillationcircuit according to the eighth embodiment of the invention;

FIG. 15 is a block diagram showing the configuration of an oscillationcircuit according to a ninth embodiment of the invention;

FIG. 16 is a block diagram showing the configuration of a pulsegeneration circuit according to a tenth embodiment of the invention;

FIG. 17 is a block diagram showing a configuration example of an SWcontrol circuit according to the tenth embodiment of the invention;

FIG. 18 is a timing chart showing the operation of the pulse generationcircuit according to the tenth embodiment of the invention;

FIG. 19 is a diagram showing a modification of a reference voltagegeneration unit according to the tenth embodiment of the invention;

FIG. 20 is a block diagram showing the configuration of a referencevoltage generation unit according to an eleventh embodiment of theinvention;

FIG. 21 is a block diagram showing the configuration of a referencevoltage generation unit according to a twelfth embodiment of theinvention;

FIG. 22 is a block diagram showing the configuration of a referencevoltage generation unit according to a thirteenth embodiment of theinvention;

FIG. 23 is a block diagram showing the configuration of a PLL accordingto a fourteenth embodiment of the invention;

FIG. 24 is a block diagram showing the configuration of a semiconductorintegrated circuit according to a fifteenth embodiment of the invention;

FIG. 25 is a block diagram showing the configuration of a semiconductorintegrated circuit according to a sixteenth embodiment of the invention;

FIG. 26 is a diagram showing a layout configuration of the oscillationcircuit according to the invention;

FIG. 27 is a diagram showing a layout configuration of the oscillationcircuit according to the invention;

FIG. 28 is a diagram showing a layout configuration of the oscillationcircuit according to the invention;

FIG. 29A is a diagram for explaining a configuration of the capacitoraccording to the invention;

FIG. 29B is a diagram for explaining a configuration of the capacitoraccording to the invention;

FIG. 30 is a block diagram showing the configuration of an oscillationcircuit according to a concept before reaching the present invention;and

FIG. 31 is a timing chart showing the operation of the oscillationcircuit according to the concept before reaching the present invention.

DETAILED DESCRIPTION

First, a configuration that the present inventors have studied beforereaching the present invention will be described before the descriptionof embodiments of the invention.

FIG. 30 is a block diagram showing the configuration of a relaxationoscillation circuit according to a concept before reaching the presentinvention. The oscillation circuit 500 shown in FIG. 30 includes an RSflip-flop 11, an electric-charge charge/discharge unit 12, a comparator(first comparator) 13, a comparator (second comparator) 14, and areference voltage generation unit 15.

The RS flip-flop 11 outputs an output signal (hereinafter referred to asan output signal Q) from an output terminal Q, and outputs an inversionsignal (hereinafter referred to as an output signal QB) of the outputsignal Q from an output terminal QB, based on an input signal(comparison result X2 described below) supplied to an input terminal Sand an input signal (comparison result Y2 described below) supplied toan input terminal R.

For example, when the input signal supplied to the input terminal Srises while the input signal supplied to the input terminal R is at an Llevel, the RS flip-flop 11 raises the output signal Q and lowers theoutput signal QB. On the other hand, when the input signal supplied tothe input terminal R rises while the input signal supplied to the inputterminal S is at the L level, the RS flip-flop 11 lowers the outputsignal Q and raises the output signal QB. The RS flip-flop 11 oscillatesthe output signals Q and QB as the respective input signals supplied tothe input terminals R and S rise alternately. The output signals Q andQB are also referred to as oscillation signals.

The electric-charge charge/discharge unit 12 charges or dischargescapacitors C1 and C2 complementarily, based on the output signals Q andQB. The electric-charge charge/discharge unit 12 has a constant currentsource circuit (second constant current source circuit) B1 for feeding aconstant current, switches SW1 to SW4, the capacitor (first capacitor)C1, and the capacitor (second capacitor) C2. The switches SW1 to SW4 arecollectively referred to as a switch unit. In this example, thecapacitors C1 and C2 have substantially the same capacitance value.

In the electric-charge charge/discharge unit 12, the input terminal ofthe constant current source circuit B1 is coupled to ahigh-potential-side supply terminal (hereinafter referred to as a powersupply voltage terminal VDD) to which a power supply voltage VDD issupplied. The output terminal of the constant current source circuit B1is coupled to one terminal of the switch SW1 and one terminal of theswitch SW3. The other terminal of the switch SW1 is coupled through anode X1 to one terminal of the switch SW2. The other terminal of theswitch SW2 is coupled to a low-potential-side supply terminal(hereinafter referred to as a ground voltage terminal GND) to which aground voltage GND is supplied. Further, the other terminal of theswitch SW3 is coupled through a node Y1 to one terminal of the switchSW4. The other terminal of the switch SW4 is coupled to the groundvoltage terminal GND. A power source for supplying a voltage to thesupply terminal (ground voltage terminal GND in FIG. 30) remote from theconstant current source circuit B1 is occasionally referred to as afirst power source.

The capacitor C1 is provided in parallel with the switch SW2, betweenthe node X1 and the ground voltage terminal GND. The capacitor C2 isprovided in parallel with the switch SW4, between the node Y1 and theground voltage terminal GND.

The switches SW1 and SW4 are turned on or off based on the output signalQB of the RS flip-flop 11. On the other hand, the switches SW2 and SW3are turned on or off based on the output signal Q of the RS flip-flop11.

For example, when the output signal Q is at the L level and the outputsignal QB is at the H level, the switches SW1 and SW4 are turned on andthe switches SW2 and SW3 are turned off. In this case, due to thecontinuity between the constant current source circuit B1 and one end(node X1) of the capacitor C1, electric charge is gradually accumulatedat the one end of the capacitor C1 by the current flowing through theconstant current source circuit B1, so that the voltage level (firstvoltage) of the node X1 gradually rises. Further, due to the continuitybetween the ground voltage terminal GND and one end (node Y1) of thecapacitor C2, electric charge accumulated at the one end of thecapacitor C2 is instantly released, so that the voltage level (secondvoltage) of the node Y1 instantly falls to the ground voltage level (Llevel).

On the other hand, when the output signal Q is at the H level and theoutput signal QB is at the L level, the switches SW1 and SW4 are turnedoff and the switches SW2 and SW3 are turned on. In this case, due to thecontinuity between the constant current source circuit B1 and the oneend (node Y1) of the capacitor C2, electric charge is graduallyaccumulated at the one end of the capacitor C2 by the current flowingthrough the constant current source circuit B1, so that the voltagelevel of the node Y1 gradually rises. Further, due to the continuitybetween the ground voltage terminal GND and the one end (node X1) of thecapacitor C1, electric charge accumulated at the one end of thecapacitor C1 is instantly released, so that the voltage level of thenode X1 instantly falls to the ground voltage level (L level).

Thus, the capacitors C1 and C2 are charged or dischargedcomplementarily, based on the output signals Q and QB of the RSflip-flop 11.

The reference voltage generation unit 15 generates a reference voltageVref having a stable voltage level. The reference voltage generationunit 15 has a constant current source circuit (third constant currentsource circuit) B3 for feeding a constant current and a resistanceelement (first resistance element) R1.

The constant current source circuit B3 and the resistance element R1 areprovided in series between the power supply voltage terminal VDD and theground voltage terminal GND. More specifically, the power supply voltageterminal VDD is coupled to the input terminal of the constant currentsource circuit B3. The output terminal of the constant current sourcecircuit B3 is coupled through a node N1 to one end of the resistanceelement R1. The other end of the resistance element R1 is coupled to theground voltage terminal GND. The voltage level of the node N1 isdetermined based on the current value of the current outputted from theconstant current source circuit B3 and the resistance value of theresistance element R1. The reference voltage generation unit 15 outputsthe voltage (second reference voltage) of the node N1 as the referencevoltage Vref.

The comparator 13 compares the reference voltage Vref and the voltagelevel of the node X1, and outputs a comparison result X2. In the exampleof FIG. 30, the comparator 13 outputs the comparison result X2 of the Hlevel when the voltage level of the node X1 reaches the referencevoltage Vref, and outputs the comparison result X2 of the L level whenthe voltage level of the node X1 is less than the reference voltageVref. The voltage (reference voltage Vref in FIG. 30) supplied to thecomparator 13 for comparison with the voltage level of the node X1 isoccasionally referred to as a first reference voltage.

The comparator 14 compares the reference voltage Vref and the voltagelevel of the node Y1, and outputs a comparison result Y2. In the exampleof FIG. 30, the comparator 14 outputs the comparison result Y2 of the Hlevel when the voltage level of the node Y1 reaches the referencevoltage Vref, and outputs the comparison result Y2 of the L level whenthe voltage level of the node Y1 is less than the reference voltageVref. The voltage (reference voltage Vref in FIG. 30) supplied to thecomparator 14 for comparison with the voltage level of the node Y1 isoccasionally referred to as the first reference voltage.

For example, when the output signal Q is at the L level and the outputsignal QB is at the H level, the switches SW1 and SW4 are turned on andthe switches SW2 and SW3 are turned off, as described above. Thereby,the capacitor C1 is charged and the voltage level of the node X1gradually rises. When the voltage level of the node X1 reaches the levelof the reference voltage Vref, the comparator 13 raises the comparisonresult X2 from the L level to the H level. At this time, the capacitorC2 is discharged; therefore, the voltage level of the node Y1 is at theL level less than the reference voltage Vref. Accordingly, thecomparator 14 outputs the comparison result Y2 of the L level.Consequently, the RS flip-flop 11 raises the output signal Q and lowersthe output signal QB.

Since the output signal Q becomes the H level and the output signal QBbecomes the L level, the switches SW1 and SW4 are turned off and theswitches SW2 and SW3 are turned on. Thereby, the capacitor C2 is chargedand the voltage level of the node Y1 gradually rises. When the voltagelevel of the node Y1 reaches the level of the reference voltage Vref,the comparator 14 raises the comparison result Y2 from the L level tothe H level. At this time, the capacitor C1 is discharged; therefore,the voltage level of the node X1 is at the L level less than thereference voltage Vref. Accordingly, the comparator 13 outputs thecomparison result X2 of the L level. Consequently, the RS flip-flop 11lowers the output signal Q and raises the output signal QB. Theseoperations are repeated.

Thus, the comparison results X2 and Y2 of the comparators 13 and 14 risealternately. The RS flip-flop 11 oscillates the output signals Q and QBas the respective input signals (comparison results X2 and Y2) suppliedto the input terminals R and S rise alternately.

In the oscillation circuit 500 shown in FIG. 30, ideally the logicvalues of the output signals Q and QB of the RS flip-flop 11 change atthe moment when the voltage level of the node X1 reaches the level ofthe reference voltage Vref or when the voltage level of the node Y1reaches the level of the reference voltage Vref. However, in reality,the logic values of the output signals Q and QB of the RS flip-flop 11change after a delay time Td caused by the operation delay of thecomparator 13, 14 and the RS flip-flop 11 has elapsed from the time whenthe voltage level of the node X1 reaches the level of the referencevoltage Vref or the time when the voltage level of the node Y1 reachesthe level of the reference voltage Vref (see FIG. 31).

The change rate (slew rate) of the voltage level of the node X1 or Y1 inan ideal state is expressed as follows.

dV/dt=I/C  (1)

where V denotes the voltage level of the node X1 or Y1, I denotes thecurrent value of the current flowing through the constant current sourcecircuit B1, and C denotes the capacitance value of the capacitor C1 orC2.

Further, the reference voltage Vref is expressed as follows.

Vref=R1·Ib  (2)

where R1 denotes the resistance value of the resistance element R1, andIb denotes the current value of the current flowing through the constantcurrent source circuit B3.

Assuming that the current values I and Ib are identical, the pulse widthTp of the output signals Q and QB in an ideal state is expressed asfollows.

Tp=C·Vref/Ib=R1·C  (3)

However, in reality, due to the influence of the operation delay of thecomparator 13, 14 and the RS flip-flop 11 as described above, the pulsewidth Tp of the output signals Q and QB is expressed as follows.

Tp=R1·C+Td  (4)

Accordingly, in the oscillation circuit 500 shown in FIG. 30, there is aproblem that the oscillation frequency of the output signals Q and QBvaries as the delay time Td varies with fluctuations in temperature orpower supply voltage. That is, there is a problem that the oscillationcircuit 500 shown in FIG. 30 cannot output oscillation signals (outputsignals Q and QB) having an accurate frequency.

Hereinafter, preferred embodiments of the invention will be describedwith reference to the accompanying drawings. Since the drawings arepresented as merely illustrative, the technical scope of the inventionshould not be interpreted restrictively on the basis of the drawings.The same components are denoted by the same reference numerals, andtheir description will not be repeated.

First Embodiment

FIG. 1 is a block diagram showing the configuration of an oscillationcircuit 1 according to a first embodiment of the invention. FIG. 2 is atiming chart showing the operation of the oscillation circuit 1according to the first embodiment of the invention. The oscillationcircuit 1 according to this embodiment can output oscillation signals(output signals Q and QB) having an accurate frequency even withfluctuations in temperature or power supply voltage. Hereinafter, theoscillation circuit 1 will be described with reference to FIGS. 1 and 2.

The oscillation circuit 1 shown in FIG. 1 includes the RS flip-flop 11,the electric-charge charge/discharge unit 12, the comparator (firstcomparator) 13, the comparator (second comparator) 14, the referencevoltage generation unit 15, a control voltage generation unit 16, and acomparison voltage generation unit (voltage control unit) 17. That is,in comparison with the oscillation circuit 500 shown in FIG. 30, theoscillation circuit 1 shown in FIG. 1 further includes the controlvoltage generation unit 16 and the comparison voltage generation unit17. The control voltage generation unit 16 and the comparison voltagegeneration unit 17 are collectively referred to as a control unit.Hereinafter, points different from the oscillation circuit 500 shown inFIG. 30 will be mainly described.

The control voltage generation unit 16 generates a control voltage Vschaving a voltage level according to the frequency of the output signalsQ and QB of the RS flip-flop 11. The control voltage generation unit 16has a constant current source circuit (first constant current sourcecircuit) B4 for feeding a constant current, a switch SW5, a switch SW6,and a capacitor C3.

The constant current source circuit B4 and the switches SW5 and SW6 areprovided in series between the power supply voltage terminal VDD and theground voltage terminal GND. More specifically, the power supply voltageterminal VDD is coupled to the input terminal of the constant currentsource circuit B4. The output terminal of the constant current sourcecircuit B4 is coupled through a node N2 to one terminal of the switchSW5. The other terminal of the switch SW5 is coupled through a node N3to one terminal of the switch SW6. The other terminal of the switch SW6is coupled to the ground voltage terminal GND. The capacitor C3 isprovided in parallel with the switch SW6, between the node N3 and theground voltage terminal GND. That is, the control voltage generationunit 16 is a so-called switched capacitor.

The switch SW5 is turned on or off, for example, based on the outputsignal Q of the RS flip-flop 11. On the other hand, the switch SW6 isturned on or off, for example, based on the output signal QB of the RSflip-flop 11. That is, the switches SW5 and SW6 are turned on or offcomplementarily.

For example, when the output signal Q is at the H level and the outputsignal QB is at the L level, the switch SW5 is turned on and the switchSW6 is turned off. In this case, due to the continuity between theconstant current source circuit B4 and one end (node N3) of thecapacitor C3, electric charge outputted from the constant current sourcecircuit B4 is accumulated at the one end of the capacitor C3, so thatthe voltage level of the node N2 rises. On the other hand, when theoutput signal Q is at the L level and the output signal QB is at the Hlevel, the switch SW5 is turned off and the switch SW6 is turned on. Inthis case, due to the continuity between the ground voltage terminal GNDand the one end of the capacitor C3, electric charge accumulated at theone end of the capacitor C3 is released, so that the voltage level ofthe node N2 falls.

Thus, the switches SW5 and SW6 are turned on and off at high speed withthe oscillation period of the output signals Q and QB, thereby forming apseudo resistance element. The resistance value Rd of the pseudoresistance element is expressed as follows.

Rd=1/(f·C3)  (5)

where f denotes the frequency of the output signals Q and QB, and C3denotes the capacitance value of the capacitor C3.

As is obvious from equation (5), the resistance value Rd of the pseudoresistance element decreases as the frequency f of the output signals Qand QB increases, and the resistance value Rd of the pseudo resistanceelement increases as the frequency f of the output signals Q and QBdecreases. The voltage level of the node N2 is determined based on thecurrent value of the current outputted from the constant current sourcecircuit B4 and the resistance value Rd of the pseudo resistance element.

Therefore, the voltage level of the node N2 decreases as the frequency fof the output signals Q and QB increases, and the voltage level of thenode N2 increases as the frequency f of the output signals Q and QBdecreases. The control voltage generation unit 16 outputs the voltage ofthe node N2 as the control voltage Vsc. That is, the control voltagegeneration unit 16 generates the control voltage Vsc whose voltage leveldecreases as the frequency f of the output signals Q and QB increasesand increases as the frequency f of the output signals Q and QBdecreases.

The comparison voltage generation unit 17 generates a comparison voltageVcmp according to the difference between the control voltage Vsc and thereference voltage Vref. The comparison voltage generation unit 17 has anoperational amplifier A1, a resistance element R4, and a capacitor C4.

One end of the resistance element R4 is coupled to the node N2 of thecontrol voltage generation unit 16, and the other end of the resistanceelement R4 is coupled to the inverting input terminal of the operationalamplifier A1. That is, the control voltage Vsc from the control voltagegeneration unit 16 is supplied through the resistance element R4 to theinverting input terminal of the operational amplifier A1. A currentproportional to the difference between the control voltage Vsc and thereference voltage Vref flows through the resistance element R4. Further,the reference voltage Vref from the reference voltage generation unit 15is supplied to the non-inverting input terminal of the operationalamplifier A1. The capacitor C4 is provided between the inverting inputterminal and the output terminal of the operational amplifier A1. Theoperational amplifier A1 outputs the comparison voltage Vcmp from theoutput terminal. The comparison voltage generation unit 17 feeds back aportion of the output of the operational amplifier A1 to the input sideso that the voltage level of the inverting input terminal of theoperational amplifier A1 becomes equal to the voltage level of thenon-inverting input terminal of the operational amplifier A1. That is,the comparison voltage generation unit 17 is a so-called integrationcircuit.

With this configuration, the comparison voltage generation unit 17generates the comparison voltage Vcmp according to the differencebetween the average value of the control voltage Vsc and the referencevoltage Vref.

The voltage level of the comparison voltage Vcmp decreases as thecontrol voltage Vsc becomes higher than the reference voltage Vref, andthe voltage level of the comparison voltage Vcmp increases as thecontrol voltage Vsc becomes lower than the reference voltage Vref.Accordingly, for example, the capacitance value of the capacitor C3 inthe control voltage generation unit 16 is adjusted beforehand so thatthe output signals Q and QB have a desired frequency when the controlvoltage Vsc becomes substantially the same voltage level as thereference voltage Vref.

Therefore, for example, when the frequency of the output signals Q andQB becomes higher than the desired frequency, the control voltage Vscbecomes lower than the reference voltage Vref, so that the comparisonvoltage Vcmp becomes higher. On the other hand, when the frequency ofthe output signals Q and QB becomes lower than the desired frequency,the control voltage Vsc becomes higher than the reference voltage Vref,so that the comparison voltage Vcmp becomes lower. When the frequency ofthe output signals Q and QB becomes equal to the desired frequency, thecontrol voltage Vsc becomes substantially the same voltage level as thereference voltage Vref.

In FIG. 1, the comparison voltage Vcmp in place of the reference voltageVref is supplied to the inverting input terminals of the comparators 13and 14. That is, the comparator 13 compares the comparison voltage Vcmpand the voltage level of the node X1, and outputs the comparison resultX2. The comparator 14 compares the comparison voltage Vcmp and thevoltage level of the node Y1, and outputs the comparison result Y2. Thevoltage (comparison voltage Vcmp in FIG. 1) supplied to the comparators13 and 14 for comparison with the voltage levels of the nodes X1 and Y1is occasionally referred to as the first reference voltage.

Consequently, when the frequency of the output signals Q and QB becomeshigher than the desired frequency and the comparison voltage Vcmpbecomes higher, the time until the voltage levels of the nodes X1 and Y1reach the comparison voltage Vcmp increases comparatively, so that thefrequency of the output signals Q and QB decreases. On the other hand,when the frequency of the output signals Q and QB becomes lower than thedesired frequency and the comparison voltage Vcmp becomes lower, thetime until the voltage levels of the nodes X1 and Y1 reach thecomparison voltage Vcmp decreases comparatively, so that the frequencyof the output signals Q and QB increases. When the frequency of theoutput signals Q and QB is equal to the desired frequency, that is, thecontrol voltage Vsc is substantially the same voltage level as thereference voltage Vref, the frequency of the output signals Q and QBmaintains the desired frequency.

Thus, the oscillation circuit 1 according to this embodiment, when thefrequency of the output signals Q and QB is higher than the desiredfrequency, increases the comparison voltage Vcmp and thereby decreasesthe frequency of the output signals Q and QB. On the other hand, theoscillation circuit 1 according to this embodiment, when the frequencyof the output signals Q and QB is lower than the desired frequency,decreases the comparison voltage Vcmp and thereby increases thefrequency of the output signals Q and QB. That is, the oscillationcircuit 1 according to this embodiment generates the comparison voltageVcmp according to the frequency of the output signals Q and QB, andthereby controls the timing at which the voltage level of the node X1becomes equal to the voltage level of the comparison voltage Vcmp andthe timing at which the voltage level of the node Y1 becomes equal tothe voltage level of the comparison voltage Vcmp. Accordingly, theoscillation circuit 1 according to this embodiment can accurately outputthe output signals (oscillation signals) Q and QB having the desiredfrequency even when the delay time Td caused by the operation delay ofthe comparator and the RS flip-flop varies with fluctuations intemperature or power supply voltage.

Second Embodiment

FIG. 3 is a block diagram showing the configuration of an oscillationcircuit 1 a according to a second embodiment of the invention. Incomparison with the oscillation circuit 1 shown in FIG. 1, theoscillation circuit 1 a shown in FIG. 3 includes an electric-chargecharge/discharge unit 12 a in place of the electric-chargecharge/discharge unit 12 and a control voltage generation unit 16 a inplace of the control voltage generation unit 16. Further, in theoscillation circuit 1 a shown in FIG. 3, unlike the oscillation circuit1 shown in FIG. 1, the voltages of the nodes X1 and Y1 are supplied tothe inverting input terminals of the comparators 13 and 14 respectively,and the comparison voltage Vcmp is supplied to the non-inverting inputterminals of the comparators 13 and 14.

In the electric-charge charge/discharge unit 12 a, the constant currentsource circuit B1 is provided on the ground voltage terminal GND side.More specifically, the power supply voltage terminal VDD is coupled toone terminal of the switch SW1 and one terminal of the switch SW3. Theother terminal of the switch SW1 is coupled through the node X1 to oneterminal of the switch SW2. The other terminal of the switch SW2 iscoupled to the input terminal of the constant current source circuit B1.Further, the other terminal of the switch SW3 is coupled through thenode Y1 to one terminal of the switch SW4. The other terminal of theswitch SW4 together with the other terminal of the switch SW2 is coupledto the input terminal of the constant current source circuit B1. Theoutput terminal of the constant current source circuit B1 is coupled tothe ground voltage terminal GND. The coupling relationship between thecapacitors C1 and C2 is the same as in FIG. 1, and will not be describedagain. A power source for supplying a voltage to the supply terminal(power supply voltage terminal VDD in FIG. 3) remote from the constantcurrent source circuit B1 is occasionally referred to as a first powersource.

In the control voltage generation unit 16 a, the constant current sourcecircuit B4 is provided on the ground voltage terminal GND side. Morespecifically, the power supply voltage terminal VDD is coupled to oneterminal of the switch SW5. The other terminal of the switch SW5 iscoupled through the node N3 to one terminal of the switch SW6. The otherterminal of the switch SW6 is coupled through the node N2 to the inputterminal of the constant current source circuit B4. The output terminalof the constant current source circuit B4 is coupled to the groundvoltage terminal GND. The capacitor C3 is provided between the node N3and the ground voltage terminal GND.

As described above, the resistance value Rd of the pseudo resistanceelement decreases as the frequency f of the output signals Q and QBincreases, and the resistance value Rd of the pseudo resistance elementincreases as the frequency f of the output signals Q and QB decreases.The voltage level of the node N2 is determined based on the currentvalue of the current outputted from the constant current source circuitB4 and the resistance value Rd of the pseudo resistance element.

Therefore, the voltage level of the node N2 increases as the frequency fof the output signals Q and QB increases, and the voltage level of thenode N2 decreases as the frequency f of the output signals Q and QBdecreases. The control voltage generation unit 16 a outputs the voltageof the node N2 as the control voltage Vsc. That is, the control voltagegeneration unit 16 a generates the control voltage Vsc whose voltagelevel increases as the frequency f of the output signals Q and QBincreases and decreases as the frequency f of the output signals Q andQB decreases.

Therefore, for example, when the frequency of the output signals Q andQB becomes higher than the desired frequency, the control voltage Vscbecomes higher than the reference voltage Vref, so that the comparisonvoltage Vcmp becomes lower. On the other hand, when the frequency of theoutput signals Q and QB becomes lower than the desired frequency, thecontrol voltage Vsc becomes lower than the reference voltage Vref, sothat the comparison voltage Vcmp becomes higher. When the frequency ofthe output signals Q and QB becomes equal to the desired frequency, thecontrol voltage Vsc becomes substantially the same voltage level as thereference voltage Vref. The remaining circuit configuration andoperation of the oscillation circuit 1 a shown in FIG. 3 are the same asthose of the oscillation circuit 1 shown in FIG. 1, and will not bedescribed again.

FIG. 4 is a timing chart showing the operation of the oscillationcircuit 1 a. For example, when the output signal Q is at the L level andthe output signal QB is at the H level, the switches SW1 and SW4 areturned on and the switches SW2 and SW3 are turned off. In this case, dueto the continuity between the power supply voltage terminal VDD and oneend (node X1) of the capacitor C1, electric charge from the power supplyvoltage terminal VDD is instantly accumulated at the one end of thecapacitor C1, so that the voltage level of the node X1 instantly risesto the power supply voltage level (H level). Further, due to thecontinuity between the constant current source circuit B1 and one end(node Y1) of the capacitor C2, electric charge accumulated at the oneend of the capacitor C2 is gradually released by the current flowingthrough the constant current source circuit B1, so that the voltagelevel of the node Y1 gradually falls.

On the other hand, when the output signal Q is at the H level and theoutput signal QB is at the L level, the switches SW1 and SW4 are turnedoff and the switches SW2 and SW3 are turned on. In this case, due to thecontinuity between the power supply voltage terminal VDD and the one end(node Y1) of the capacitor C2, electric charge from the power supplyvoltage terminal VDD is instantly accumulated at the one end of thecapacitor C2, so that the voltage level of the node Y1 instantly risesto the power supply voltage level (H level). Further, due to thecontinuity between the constant current source circuit B1 and the oneend (node X1) of the capacitor C1, electric charge accumulated at theone end of the capacitor C1 is gradually released by the current flowingthrough the constant current source circuit B1, so that the voltagelevel of the node X1 gradually falls.

The comparator 13 outputs the comparison result X2 of the H level whenthe voltage level of the node X1 falls and reaches the level of thecomparison voltage Vcmp, and outputs the comparison result X2 of the Llevel when the voltage level of the node X1 is higher than thecomparison voltage Vcmp. The comparator 14 outputs the comparison resultY2 of the H level when the voltage level of the node Y1 falls andreaches the level of the comparison voltage Vcmp, and outputs thecomparison result Y2 of the L level when the voltage level of the nodeY1 is higher than the comparison voltage Vcmp.

Consequently, when the frequency of the output signals Q and QB becomeshigher than the desired frequency and the comparison voltage Vcmpbecomes lower, the time until the voltage levels of the nodes X1 and Y1fall and reach the comparison voltage Vcmp increases comparatively, sothat the frequency of the output signals Q and QB decreases. On theother hand, when the frequency of the output signals Q and QB becomeslower than the desired frequency and the comparison voltage Vcmp becomeshigher, the time until the voltage levels of the nodes X1 and Y1 falland reach the comparison voltage Vcmp decreases comparatively, so thatthe frequency of the output signals Q and QB increases. When thefrequency of the output signals Q and QB is equal to the desiredfrequency, that is, the control voltage Vsc is substantially the samevoltage level as the reference voltage Vref, the frequency of the outputsignals Q and QB maintains the desired frequency.

With this circuit configuration, the oscillation circuit 1 a shown inFIG. 3 can provide the same effect as the oscillation circuit 1 shown inFIG. 1. In the following embodiments as well, this change in circuitconfiguration can be made as appropriate without departing from thespirit and scope of the invention.

Third Embodiment

FIG. 5 is a block diagram showing the configuration of an oscillationcircuit 1 b according to a third embodiment of the invention. FIG. 6 isa timing chart showing the operation of the oscillation circuit 1 baccording to the third embodiment of the invention. In comparison withthe oscillation circuit 1 shown in FIG. 1, the oscillation circuit 1 bshown in FIG. 5 includes an electric-charge charge/discharge unit 12 bin place of the electric-charge charge/discharge unit 12. Further, inthe oscillation circuit 1 b shown in FIG. 5, unlike the oscillationcircuit 1 shown in FIG. 1, the reference voltage Vref is supplied to theinverting input terminals of the comparators 13 and 14. Therefore, thecomparators 13 and 14 compare the voltages of the nodes X1, Y1 and theconstant reference voltage Vref, respectively. Further, the comparisonvoltage Vcmp generated by the comparison voltage generation unit 17 issupplied to the electric-charge charge/discharge unit 12 b. Hereinafter,the oscillation circuit 1 b will be described with reference to FIGS. 5and 6.

In comparison with the electric-charge charge/discharge unit 12, theelectric-charge charge/discharge unit 12 b has a variable current sourcecircuit B1 b in place of the constant current source circuit B1. Thevariable current source circuit B1 b feeds a current according to thecomparison voltage Vcmp. For example, the current flowing through thevariable current source circuit B1 b decreases as the comparison voltageVcmp increases, and increases as the comparison voltage Vcmp decreases.

For example, when the frequency of the output signals Q and QB becomeshigher than the desired frequency and the control voltage Vsc becomeslower than the reference voltage Vref, the current flowing through thevariable current source circuit B1 b decreases. This decreases thecharging rate of the capacitors C1 and C2; therefore, the time until thevoltage levels of the nodes X1 and Y1 reach the level of the referencevoltage Vref increases comparatively, so that the frequency of theoutput signals Q and QB decreases. On the other hand, when the frequencyof the output signals Q and QB becomes lower than the desired frequencyand the control voltage Vsc becomes higher than the reference voltageVref, the current flowing through the variable current source circuitBib increases. This increases the charging rate of the capacitors C1 andC2; therefore, the time until the voltage levels of the nodes X1 and Y1reach the level of the reference voltage Vref decreases comparatively,so that the frequency of the output signals Q and QB increases. When thefrequency of the output signals Q and QB is equal to the desiredfrequency, that is, the control voltage Vsc is substantially the samevoltage level as the reference voltage Vref, the frequency of the outputsignals Q and QB maintains the desired frequency.

Thus, the oscillation circuit 1 b according to this embodiment, when thefrequency of the output signals Q and QB is higher than the desiredfrequency, decreases the current flowing through the variable currentsource circuit B1 b and decreases the rise rate (slew rate) of thevoltage levels of the nodes X1 and Y1, thereby decreasing the frequencyof the output signals Q and QB. On the other hand, the oscillationcircuit 1 b according to this embodiment, when the frequency of theoutput signals Q and QB is lower than the desired frequency, increasesthe current flowing through the variable current source circuit Bib andincreases the rise rate (slew rate) of the voltage levels of the nodesX1 and Y1, thereby increasing the frequency of the output signals Q andQB. That is, the oscillation circuit 1 b according to this embodimentcauses the variable current source circuit B1 b to feed the currentaccording to the frequency of the output signals Q and QB, and therebycontrols the timing at which the voltage level of the node X1 becomesequal to the voltage level of the reference voltage Vref and the timingat which the voltage level of the node Y1 becomes equal to the voltagelevel of the reference voltage Vref. Accordingly, the oscillationcircuit 1 b according to this embodiment can accurately output theoutput signals (oscillation signals) Q and QB having the desiredfrequency even when the delay time Td caused by the operation delay ofthe comparator and the RS flip-flop varies with fluctuations intemperature or power supply voltage.

Fourth Embodiment

FIG. 7 is a block diagram showing the configuration of an oscillationcircuit 1 c according to a fourth embodiment of the invention. Incomparison with the oscillation circuit 1 shown in FIG. 1, theoscillation circuit 1 c shown in FIG. 7 includes an electric-chargecharge/discharge unit 12 c in place of the electric-chargecharge/discharge unit 12. Further, in the oscillation circuit 1 c shownin FIG. 7, unlike the oscillation circuit 1 shown in FIG. 1, thereference voltage Vref is supplied to the inverting input terminals ofthe comparators 13 and 14. Therefore, the comparators 13 and 14 comparethe voltages of the nodes X1, Y1 and the constant reference voltageVref, respectively. Further, the comparison voltage Vcmp generated bythe comparison voltage generation unit 17 is supplied to theelectric-charge charge/discharge unit 12 c.

In comparison with the electric-charge charge/discharge unit 12, theelectric-charge charge/discharge unit 12 c has variable capacitors C1 cand C2 c in place of the capacitors C1 and C2. The variable capacitorsC1 c and C2 c have variable capacitance values according to thecomparison voltage Vcmp. For example, the capacitances of the variablecapacitors C1 c and C2 c increase as the comparison voltage Vcmpincreases, and decrease as the comparison voltage Vcmp decreases.

For example, when the frequency of the output signals Q and QB becomeshigher than the desired frequency and the control voltage Vsc becomeslower than the reference voltage Vref, the capacitance values of thevariable capacitors C1 c and C2 c increase. Accordingly, the time untilthe voltage levels of the nodes X1 and Y1 reach the level of thereference voltage Vref increases comparatively, so that the frequency ofthe output signals Q and QB decreases. On the other hand, when thefrequency of the output signals Q and QB becomes lower than the desiredfrequency and the control voltage Vsc becomes higher than the referencevoltage Vref, the capacitance values of the variable capacitors C1 c andC2 c decrease. Accordingly, the time until the voltage levels of thenodes X1 and Y1 reach the level of the reference voltage Vref decreasescomparatively, so that the frequency of the output signals Q and QBincreases. When the frequency of the output signals Q and QB is equal tothe desired frequency, that is, the control voltage Vsc is substantiallythe same voltage level as the reference voltage Vref, the frequency ofthe output signals Q and QB maintains the desired frequency.

Thus, the oscillation circuit 1 c according to this embodiment, when thefrequency of the output signals Q and QB is higher than the desiredfrequency, increases the capacitance values of the variable capacitorsC1 c and C2 c and decreases the rise rate (slew rate) of the voltagelevels of the nodes X1 and Y1, thereby decreasing the frequency of theoutput signals Q and QB. On the other hand, the oscillation circuit 1 caccording to this embodiment, when the frequency of the output signals Qand QB is lower than the desired frequency, decreases the capacitancevalues of the variable capacitors C1 c and C2 c and increases the riserate (slew rate) of the voltage levels of the nodes X1 and Y1, therebyincreasing the frequency of the output signals Q and QB. That is, theoscillation circuit 1 c according to this embodiment controls thecapacitance values of the variable capacitors C1 c and C2 c inaccordance with the frequency of the output signals Q and QB, andthereby controls the timing at which the voltage level of the node X1becomes equal to the voltage level of the reference voltage Vref and thetiming at which the voltage level of the node Y1 becomes equal to thevoltage level of the reference voltage Vref. Accordingly, theoscillation circuit 1 c according to this embodiment can accuratelyoutput the output signals (oscillation signals) Q and QB having thedesired frequency even when the delay time Td caused by the operationdelay of the comparator and the RS flip-flop varies with fluctuations intemperature or power supply voltage.

Fifth Embodiment

FIG. 8 is a block diagram showing the configuration of an oscillationcircuit 1 d according to a fifth embodiment of the invention. Incomparison with the oscillation circuit 1 shown in FIG. 1, theoscillation circuit 1 d shown in FIG. 8 includes one electric-chargecharge/discharge and control voltage generation unit 18 in place of theelectric-charge charge/discharge unit 12 and the control voltagegeneration unit 16. The electric-charge charge/discharge and controlvoltage generation unit 18 has the respective functions of theelectric-charge charge/discharge unit 12 and the control voltagegeneration unit 16.

The electric-charge charge/discharge and control voltage generation unit18 charges or discharges the capacitors C1 and C2 complementarily basedon the output signals Q and QB, and generates the control voltage Vschaving a voltage level according to the frequency of the output signalsQ and QB.

The electric-charge charge/discharge and control voltage generation unit18 has the constant current source circuit B1 for feeding a constantcurrent, the switches SW1 to SW4, and the capacitors C1 and C2.

The power supply voltage terminal VDD is coupled to the input terminalof the constant current source circuit B1. The output terminal of theconstant current source circuit B1 is coupled through a node N4 to oneterminal of the switch SW1 and one terminal of the switch SW3. The otherterminal of the switch SW1 is coupled through the node X1 to oneterminal of the switch SW2. The other terminal of the switch SW2 iscoupled to the ground voltage terminal GND. The other terminal of theswitch SW3 is coupled through the node Y1 to one terminal of the switchSW4. The other terminal of the switch SW4 is coupled to the groundvoltage terminal GND.

The capacitor C1 is provided in parallel with the switch SW2, betweenthe node X1 and the ground voltage terminal GND. The capacitor C2 isprovided in parallel with the switch SW4, between the node Y1 and theground voltage terminal GND.

In the electric-charge charge/discharge and control voltage generationunit 18, the constant current source circuit B1 corresponds to theconstant current source circuit B4 in the control voltage generationunit 16, the switches SW1 and SW3 correspond to the switch SW5 in thecontrol voltage generation unit 16, the switches SW2 and SW4 correspondto the switch SW6 in the control voltage generation unit 16, and thecapacitors C1 and C2 correspond to the capacitor C3 in the controlvoltage generation unit 16. The electric-charge charge/discharge andcontrol voltage generation unit 18 outputs the voltage of the node N4 asthe control voltage Vsc.

Similarly, in the electric-charge charge/discharge and control voltagegeneration unit 18, the constant current source circuit B1 correspondsto the constant current source circuit B1 in the electric-chargecharge/discharge unit 12, the switches SW1 to SW4 correspond to theswitches SW1 to SW4 in the electric-charge charge/discharge unit 12, andthe capacitors C1 and C2 correspond to the capacitors C1 and C2 in theelectric-charge charge/discharge unit 12.

The operation of the electric-charge charge/discharge and controlvoltage generation unit 18 is the same as those of the electric-chargecharge/discharge unit 12 and the control voltage generation unit 16, andwill not be described again.

Thus, the oscillation circuit 1 d according to this embodiment, when thefrequency of the output signals Q and QB is higher than the desiredfrequency, increases the comparison voltage Vcmp and thereby decreasesthe frequency of the output signals Q and QB. On the other hand, theoscillation circuit 1 d according to this embodiment, when the frequencyof the output signals Q and QB is lower than the desired frequency,decreases the comparison voltage Vcmp and thereby increases thefrequency of the output signals Q and QB. Accordingly, the oscillationcircuit 1 d according to this embodiment can accurately output theoutput signals (oscillation signals) Q and QB having the desiredfrequency even when the delay time Td caused by the operation delay ofthe comparator and the RS flip-flop varies with fluctuations intemperature or power supply voltage.

Further, in the oscillation circuit 1 d according to this embodiment,since the constant current source circuit, the switches, and thecapacitors are shared to implement the respective functions of theelectric-charge charge/discharge unit 12 and the control voltagegeneration unit 16, it is possible to reduce the circuit size and powerconsumption.

Furthermore, in the oscillation circuit 1 d according to thisembodiment, since the constant current source circuit, the switches, andthe capacitors are shared to implement the respective functions of theelectric-charge charge/discharge unit 12 and the control voltagegeneration unit 16, for example it is possible to eliminate the errorbetween current values that can be caused by the constant current sourcecircuits provided separately.

While this embodiment has been described by way of example in which theelectric-charge charge/discharge unit 12 and the control voltagegeneration unit 16 in the oscillation circuit 1 shown in FIG. 1 arereplaced with the one electric-charge charge/discharge and controlvoltage generation unit 18, the invention is not limited thereto.Similarly, the same effect can be obtained by replacing theelectric-charge charge/discharge unit 12 b and the control voltagegeneration unit 16 in the oscillation circuit 1 b shown in FIG. 5 withthe one electric-charge charge/discharge and control voltage generationunit 18.

Sixth Embodiment

FIG. 9 is a block diagram showing the configuration of an oscillationcircuit 1 e according to a sixth embodiment of the invention. Incomparison with the oscillation circuit 1 d shown in FIG. 8, theoscillation circuit 1 e shown in FIG. 9 includes a reference voltagegeneration unit 15 e in place of the reference voltage generation unit15.

The reference voltage generation unit 15 e has the constant currentsource circuit B3 and a variable resistance element R1 e. That is, incomparison with the reference voltage generation unit 15, the referencevoltage generation unit 15 e has the variable resistance element R1 e inplace of the resistance element R1. The variable resistance element R1 ehas a variable resistance value according to a control signal Ctrl1.

Thus, the reference voltage generation unit 15 e can generate thereference voltage Vref having a desired voltage level by adjusting theresistance value of the variable resistance element R1 e based on thecontrol signal Ctrl1. Accordingly, the oscillation circuit 1 e accordingto this embodiment can freely vary the oscillation frequency of theoutput signals (oscillation signals) Q and QB. Further, even if thecurrent values of the constant current source circuits or thecapacitance values of the capacitors have become different from intendedvalues due to process variation, the oscillation circuit 1 e accordingto this embodiment can adjust the oscillation frequency of the outputsignals (oscillation signals) Q and QB to the desired value by adjustingthe resistance value of the variable resistance element R1 e based onthe control signal Ctrl1.

FIG. 10 is a diagram for explaining the control signal Ctrl1 supplied tothe reference voltage generation unit 15 e. As shown in FIG. 10, forexample a register M1 e is provided in the oscillation circuit 1 e or asemiconductor integrated circuit including the oscillation circuit 1 e.The register M1 e stores information of a control signal (externalcontrol signal) supplied from outside, and outputs the control signalCtrl1 based on the stored information. Thus, in the oscillation circuit1 e according to this embodiment, it is possible to externally controlthe control signal Ctrl1; therefore, it is possible to vary theoscillation frequency of the output signals (oscillation signals) Q andQB even after production. The register M1 e may generate the controlsignal Ctrl1 according to a request from a CPU in place of the externalcontrol signal. Further, the register M1 e may be a memory element suchas flash memory.

Similarly, the same effect can be obtained by replacing the resistanceelement R1 of the reference voltage generation unit 15 in theoscillation circuits according to the above-described embodiments withthe variable resistance element R1 e.

Seventh Embodiment

FIG. 11 is a block diagram showing the configuration of an oscillationcircuit 1 f according to a seventh embodiment of the invention. Incomparison with the oscillation circuit 1 d shown in FIG. 8, theoscillation circuit 1 f shown in FIG. 11 includes a reference voltagegeneration unit 15 f in place of the reference voltage generation unit15.

The reference voltage generation unit 15 f has the constant currentsource circuit B3, a variable resistance element (first resistanceelement) R1 f, and a variable resistance element (second resistanceelement) R2 f. That is, in comparison with the reference voltagegeneration unit 15, the reference voltage generation unit 15 f has thevariable resistance elements R1 f and R2 f in place of the resistanceelement R1. More specifically, the power supply voltage terminal VDD iscoupled to the input terminal of the constant current source circuit B3.The output terminal of the constant current source circuit B3 is coupledthrough the node N1 to one terminal of the variable resistance elementR1 f. The other terminal of the variable resistance element R1 f iscoupled to one terminal of the variable resistance element R2 f. Theother terminal of the variable resistance element R2 f is coupled to theground voltage terminal GND. The reference voltage generation unit 15 foutputs the voltage of the node N1 as the reference voltage Vref.

The variable resistance element R1 f has a variable resistance valueaccording to a control signal Ctrl1. Further, the variable resistanceelement R1 f has a positive temperature dependence in which theresistance value increases with increasing temperature. The variableresistance element R2 f has a variable resistance value according to acontrol signal Ctrl2. Further, the variable resistance element R2 f hasa negative temperature dependence in which the resistance valuedecreases with increasing temperature.

Thus, the reference voltage generation unit 15 f can generate thereference voltage Vref having a desired voltage level by adjusting theresistance values of the variable resistance elements R1 f and R2 fbased on the control signals Ctrl1 and Ctrl2 respectively. Accordingly,the oscillation circuit 1 f according to this embodiment can freely varythe oscillation frequency of the output signals (oscillation signals) Qand QB. Further, even if the current values of the constant currentsource circuits or the capacitance values of the capacitors have becomedifferent from the intended value due to process variation, theoscillation circuit 1 f according to this embodiment can adjust theoscillation frequency of the output signals (oscillation signals) Q andQB to the desired value by adjusting the resistance values of thevariable resistance elements R1 f and R2 f based on the control signalsCtrl1 and Ctrl2 respectively.

Further, since the reference voltage generation unit 15 f has thevariable resistance elements R1 f and R2 f having the differenttemperature dependences, the reference voltage generation unit 15 f cancancel resistance value change caused by temperature fluctuation.Therefore, the reference voltage generation unit 15 f can generate thestable reference voltage Vref even with fluctuations in temperature.

FIG. 12 is a diagram for explaining the control signals Ctrl1 and Ctrl2supplied to the reference voltage generation unit 15 f. As shown in FIG.12, for example a register M2 f is provided in the oscillation circuit 1f or a semiconductor integrated circuit including the oscillationcircuit 1 f. The register M2 f stores information of a control signal(external control signal) supplied from outside, and outputs the controlsignals Ctrl1 and Ctrl2 based on the stored information. Thus, in theoscillation circuit 1 f according to this embodiment, it is possible toexternally control the control signals Ctrl1 and Ctrl2; therefore, it ispossible to vary the oscillation frequency of the output signals(oscillation signals) Q and QB even after production. The register M2 fmay generate the control signals Ctrl1 and Ctrl2 according to a requestfrom the CPU in place of the external control signal. Further, theregister M2 f may be a memory element such as flash memory.

Similarly, the same effect can be obtained by replacing the resistanceelement R1 of the reference voltage generation unit 15 in theoscillation circuits according to the above-described embodiments withthe variable resistance elements R1 f and R2 f.

Eighth Embodiment

FIG. 13 is a block diagram showing the configuration of an oscillationcircuit 1 g according to an eighth embodiment of the invention. Incomparison with the oscillation circuit 1 b shown in FIG. 5, theoscillation circuit 1 g shown in FIG. 13 includes an electric-chargecharge/discharge unit 12 g in place of the electric-chargecharge/discharge unit 12 b and a pulse generation circuit (control unit)19 in place of the control voltage generation unit 16 and the comparisonvoltage generation unit 17.

The electric-charge charge/discharge unit 12 g has a variable currentsource circuit B1 g, the switches SW1 to SW4, and the capacitors C1 andC2. That is, the electric-charge charge/discharge unit 12 b has avariable current source circuit B1 g in place of the constant currentsource circuit B1. The variable current source circuit B1 g feeds acurrent according to a control signal (current control signal) Vctrloutputted from the pulse generation circuit 19. For example, when thevoltage level of the control signal Vctrl is at the L level (secondlogic value), a current having a current value I flows through thevariable current source circuit B1 g. On the other hand, when thevoltage level of the control signal Vctrl is at the H level (first logicvalue), a current having a current value 2I (two times the current valueI) flows through the variable current source circuit Big. The rise rate(slew rate) of the voltage levels of the nodes X1 and Y1 when thecurrent having the current value 2I flows through the variable currentsource circuit Big is two times the rise rate (slew rate) of the voltagelevels of the nodes X1 and Y1 when the current having the current valueI flows through the variable current source circuit Big.

The pulse generation circuit 19 generates the control signal Vctrlhaving substantially the same pulse width as the delay time Td insynchronization with the logic value changes of the output signals Q andQB. In other words, the pulse generation circuit 19 raises the controlsignal Vctrl in synchronization with the logic value changes of theoutput signals Q and QB, and lowers the control signal Vctrl after thelapse of the delay time Td. Since the period of the output signals Q andQB varies depending on the delay time Td, it can also be said that thepulse generation circuit 19 generates the control signal Vctrl havingthe pulse width according to the period of the output signals Q and QB.

FIG. 14 is a timing chart showing the operation of the oscillationcircuit 1 g shown in FIG. 13. In the example of FIG. 14, at time t0,since the output signal Q is at the H level and the output signal QB isat the L level, the switches SW1 and SW4 are turned off and the switchesSW2 and SW3 are turned on. Accordingly, the voltage level (secondvoltage) of the node Y1 gradually rises, whereas the voltage level(first voltage) of the node X1 is at the ground voltage level (L level).When the voltage level of the node Y1 reaches the reference voltage Vref(time t1), the comparator 14 raises the comparison result Y2 with alittle delay. At this time, the comparator 13 outputs the comparisonresult X2 of the L level. Consequently, the RS flip-flop 11 lowers theoutput signal Q and raises the output signal QB (time t2). In otherwords, when the voltage level of the node Y1 reaches the referencevoltage Vref (time t1), after the lapse of the delay time Td caused bythe operation delay of the comparator 14 and the RS flip-flop 11, theoutput signal Q falls and the output signal QB rises (time t2).

Since the output signal Q is at the L level and the output signal QB isat the H level, the switches SW1 and SW4 are turned on and the switchesSW2 and SW3 are turned off (time t2). Accordingly, the voltage level ofthe node X1 gradually rises, whereas the voltage level of the node Y1 isat the ground voltage level (L level). At this time, the pulsegeneration circuit 19 raises the control signal Vctrl in synchronizationwith the logic value changes of the output signals Q and QB (time t2).Then, the pulse generation circuit 19 lowers the control signal Vctrlafter the lapse of the delay time Td (time t3). That is, the pulsegeneration circuit 19 outputs the control signal Vctrl havingsubstantially the same pulse width as the delay time Td insynchronization with the logic value changes of the output signals Q andQB.

During the duration when the voltage level of the control signal Vctrlis at the H level (time t2 to time t3), the current having the currentvalue 2I flows through the variable current source circuit B1 g, so thatthe voltage level of the node X1 rises at twice the normal rate (slewrate). After the control signal Vctrl falls (time t3 to time t5), thecurrent having the normal current value I flows through the variablecurrent source circuit B1 g, so that the voltage level of the node X1rises at the normal rate (slew rate).

When the voltage level of the node X1 reaches the reference voltage Vref(time t4), the comparator 13 raises the comparison result X2 with alittle delay. At this time, the comparator 14 outputs the comparisonresult Y2 of the L level. Consequently, the RS flip-flop 11 raises theoutput signal Q and lowers the output signal QB (time t5). In otherwords, when the voltage level of the node X1 reaches the referencevoltage Vref (time t4), after the lapse of the delay time Td caused bythe operation delay of the comparator 13 and the RS flip-flop 11, theoutput signal Q rises and the output signal QB falls (time t5).

The voltage level Vx1 of the node X1 at the time (t3) when the controlsignal Vctrl falls is expressed as follows.

Vx1=2I·Td/C1  (6)

where C1 denotes the capacitance value of the capacitor C1.

The difference voltage between the reference voltage Vref and thevoltage level Vx1 of the node X1 is expressed as follows.

Vref−Vx1=Vref−2I·Td/C1  (7)

Therefore, the duration Tx from when the logic values of the outputsignals Q and QB change at time t2 to when the logic values change againat time t5 is expressed as follows.

$\begin{matrix}\begin{matrix}{{Tx} = {{Td} + {C\; {{1/I} \cdot \left( {{Vref} - {2{I \cdot {{Td}/C}}\; 1}} \right)}} + {Td}}} \\{= {C\; {1 \cdot {{Vref}/I}}}} \\{= {{RC}\; 1}}\end{matrix} & (8)\end{matrix}$

As is obvious from equation (8), the duration Tx is determinedindependent of the delay time Td.

Then, since the output signal Q is at the H level and the output signalQB is at the L level, the switches SW1 and SW4 are turned off and theswitches SW2 and SW3 are turned on (time t5). Accordingly, the voltagelevel of the node Y1 gradually rises, whereas the voltage level of thenode X1 is at the ground voltage level (L level). At this time, thepulse generation circuit 19 raises the control signal Vctrl insynchronization with the logic value changes of the output signals Q andQB (time t5). Then, the pulse generation circuit 19 lowers the controlsignal Vctrl after the lapse of the delay time Td (time t6). That is,the pulse generation circuit 19 outputs the control signal Vctrl havingsubstantially the same pulse width as the delay time Td insynchronization with the logic value changes of the output signals Q andQB.

During the duration when the voltage level of the control signal Vctrlis at the H level (time t5 to time t6), the current having the currentvalue 2I flows through the variable current source circuit B1 g, so thatthe voltage level of the node Y1 rises at twice the normal rate (slewrate). After the control signal Vctrl falls (time t6 to time t8), thecurrent having the normal current value I flows through the variablecurrent source circuit B1 g, so that the voltage level of the node Y1rises at the normal rate (slew rate).

When the voltage level of the node Y1 reaches the reference voltage Vref(time t7), the comparator 14 raises the comparison result Y2 with alittle delay. At this time, the comparator 13 outputs the comparisonresult X2 of the L level. Consequently, the RS flip-flop 11 raises theoutput signal Q and lowers the output signal QB (time t8). In otherwords, when the voltage level of the node Y1 reaches the referencevoltage Vref (time t7), after the lapse of the delay time Td caused bythe operation delay of the comparator 14 and the RS flip-flop 11, theoutput signal Q falls and the output signal QB rises (time t8). Theseoperations are repeated.

With reference to equation (6) to equation (8), the duration Ty fromwhen the logic values of the output signals Q and QB change at time t5to when the logic values change again at time t8 is expressed asfollows.

$\begin{matrix}\begin{matrix}{{Ty} = {{Td} + {C\; {{2/I} \cdot \left( {{Vref} - {2{I \cdot {{Td}/C}}\; 2}} \right)}} + {Td}}} \\{= {C\; {2 \cdot {{Vref}/I}}}} \\{= {{RC}\; 2}}\end{matrix} & (9)\end{matrix}$

where C2 denotes the capacitance value of the capacitor C2.

As is obvious from equation (9), the duration Ty is determinedindependent of the delay time Td.

Thus, the timings of the logic value changes of the output signals Q andQB are determined independent of the delay time Td. That is, even whenthe delay time Td caused by the operation delay of the comparator andthe RS flip-flop varies with fluctuations in temperature or power supplyvoltage, the oscillation circuit 1 g according to this embodiment canaccurately output the output signals (oscillation signals) Q and QBhaving the desired frequency without being influenced by fluctuations inthe delay time Td.

Further, the oscillation circuit 1 g according to this embodiment canoperate without being influenced by fluctuations in the delay time Tdfrom the initial stage (e.g., first cycle) of the oscillation, which canquickly stabilize the oscillation of the output signals Q and QB.

While this embodiment has been described by way of example in which thepulse width (duration of the H level in this example) of the controlsignal Vctrl is substantially the same as the delay time Td, theinvention is not limited thereto. The pulse width of the control signalVctrl can be modified as appropriate within the scope of smallvariations in the durations Tx and Ty according to fluctuations in thedelay time Td. In this case, although the oscillation circuit accordingto the invention might operate under the influence of fluctuations inthe delay time Td, the influence can be reduced.

Further, while this embodiment has been described by way of example inwhich twice the normal current flows through the variable current sourcecircuit B1 g while the control signal Vctrl is asserted (the voltagelevel of the control signal Vctrl is at the H level in this example),the invention is not limited thereto. The current value of the currentflowing through the variable current source circuit B1 g while thecontrol signal Vctrl is asserted can be modified as appropriate withinthe scope of small variations in the durations Tx and Ty according tofluctuations in the delay time Td. In this case, although theoscillation circuit according to the invention might operate under theinfluence of fluctuations in the delay time Td, the influence can bereduced.

Ninth Embodiment

FIG. 15 is a block diagram showing the configuration of an oscillationcircuit 1 h according to a ninth embodiment of the invention. Incomparison with the oscillation circuit 1 g shown in FIG. 13, theoscillation circuit 1 h shown in FIG. 15 includes an electric-chargecharge/discharge unit 12 h in place of the electric-chargecharge/discharge unit 12 g. The oscillation circuit 1 h shown in FIG. 15is a more specific configuration example of the oscillation circuit 1 gshown in FIG. 13.

In comparison with the electric-charge charge/discharge unit 12 g, theelectric-charge charge/discharge unit 12 h has constant current sourcecircuits B1 and B2 and a switch SW7 in place of the variable currentsource circuit B1 g. The input terminal of the constant current sourcecircuit B1 is coupled to the power supply voltage terminal VDD, and theoutput terminal of the constant current source circuit B1 is coupled toone terminal of the switch SW1 and one terminal of the switch SW3. Theinput terminal of the constant current source circuit B2 is coupled tothe power supply voltage terminal VDD, and the output terminal of theconstant current source circuit B2 is coupled to one terminal of theswitch SW7. The other terminal of the switch SW7 is coupled to the oneterminal of the switch SW1 and the one terminal of the switch SW3. Thecurrent having the current value I flows through each of the constantcurrent source circuits B1 and B2. The switch SW7 is turned on or offbased on the control signal Vctrl from the pulse generation circuit 19.The remaining circuit configuration of the electric-chargecharge/discharge unit 12 h is the same as that of the electric-chargecharge/discharge unit 12 g, and will not be described again.

For example, when the voltage level of the control signal Vctrl is atthe H level, the switch SW7 is turned on, so that the current having thecurrent value 2I flows through the node X1 or Y1. On the other hand,when the voltage level of the control signal Vctrl is at the L level,the switch SW7 is turned off, so that the current having the currentvalue I flows through the node X1 or Y1. The remaining circuitconfiguration and operation of the oscillation circuit 1 h shown in FIG.15 are the same as those of the oscillation circuit 1 g shown in FIG.13, and will not be described again.

With this circuit configuration, the oscillation circuit 1 h shown inFIG. 15 can provide the same effect as the oscillation circuit 1 g shownin FIG. 13. Further, the current value of the current flowing throughthe constant current source circuit B2 can be modified as appropriatewithin the scope of small variations in the durations Tx and Tyaccording to fluctuations in the delay time Td. In this case, althoughthe oscillation circuit according to the invention might operate underthe influence of fluctuations in the delay time Td, the influence can bereduced.

Tenth Embodiment

In this embodiment, a specific example of the pulse generation circuit19 shown in FIGS. 13 and 15 will be described. Hereinafter, descriptionwill be made of the pulse generation circuit 19 which outputs thecontrol signal Vctrl having substantially the same pulse width as thedelay time Td in synchronization with the logic value changes of theoutput signals Q and QB.

FIG. 16 is a block diagram showing a specific configuration example ofthe pulse generation circuit 19. As shown in FIG. 16, the pulsegeneration circuit 19 has an RS flip-flop 191, an electric-chargecharge/discharge unit 192, a comparator 193, a comparator 194, an SWcontrol circuit 195, capacitors C3D and C4D, and switches SW5D and SW6D.The RS flip-flop 191 corresponds to the RS flip-flop 11 in theoscillation circuit 1 g, the electric-charge charge/discharge unit 192corresponds to the electric-charge charge/discharge unit 12 g in theoscillation circuit 1 g, and the comparators 193 and 194 respectivelycorrespond to the comparators 13 and 14 in the oscillation circuit 1 g.

The pulse generation circuit 19 is configured so that the RS flip-flop191 outputs signals (oscillation signals) QD and QBD havingsubstantially the same frequency as the output signals Q and QB.Further, the pulse generation circuit 19 is configured so that a delaytime caused by the operation delay of the comparator 193, 194 and the RSflip-flop 191 is substantially the same as the delay time Td caused bythe operation delay of the comparator 13, 14 and the RS flip-flop 11.Therefore, for example, the comparators 193 and 194 and the RS flip-flop191 have the same configurations as the comparators 13 and 14 and the RSflip-flop 11, respectively.

The RS flip-flop 191 outputs the output signal QD from the outputterminal Q, and outputs the output signal QBD (inversion signal of theoutput signal QD) from the output terminal QB, based on an input signal(comparison result P3 described below) supplied to the input terminal Sand an input signal (comparison result Q3 described below) supplied tothe input terminal R. The basic operation of the RS flip-flop 191 is thesame as that of the RS flip-flop 11.

The SW control circuit 195 outputs switching signals S1 to S4 and thecontrol signal Vctrl, based on the output signals QD and QBD of the RSflip-flop 191 and the output signals Q and QB of the RS flip-flop 11.

FIG. 17 is a block diagram showing a specific configuration example ofthe SW control circuit 195. As shown in FIG. 17, the SW control circuit195 has AND circuits 1951 to 1954 and an OR circuit 1955. The ANDcircuit 1951 outputs the logical AND between the output signal QBD andthe output signal Q as the switching signal S1. The AND circuit 1952outputs the logical AND between the output signal QD and the outputsignal Q as the switching signal S2. The AND circuit 1953 outputs thelogical AND between the output signal QD and the output signal QB as theswitching signal S3. The AND circuit 1954 outputs the logical ANDbetween the output signal QBD and the output signal QB as the switchingsignal S4. Then, the OR circuit 1955 outputs the logical OR between theswitching signal S1 and the switching signal S3 as the control signalVctrl.

Referring back to FIG. 16, the electric-charge charge/discharge unit 192charges or discharges the capacitors C1D and C2D complementarily basedon the switching signals S1 to S4 from the SW control circuit 195. Theelectric-charge charge/discharge unit 192 has a constant current sourcecircuit BUD for feeding a constant current, switches SW1D to SW4D, andcapacitors C1D and C2D.

The power supply voltage terminal VDD is coupled to the input terminalof the constant current source circuit B1D. The output terminal of theconstant current source circuit B1D is coupled to one terminal of theswitch SW1D and one terminal of the switch SW3D. The other terminal ofthe switch SW1D is coupled through a node P1 to one terminal of theswitch SW2D. The other terminal of the switch SW2D is coupled to theground voltage terminal GND. The other terminal of the switch SW3D iscoupled through a node Q1 to one terminal of the switch SW4D. The otherterminal of the switch SW4D is coupled to the ground voltage terminalGND.

The capacitor C1D is provided in parallel with the switch SW2D, betweenthe node P1 and the ground voltage terminal GND. The capacitor C2D isprovided in parallel with the switch SW4D, between the node Q1 and theground voltage terminal GND.

The switches SW1D and SW4D are turned on or off based on the switchingsignals S1 to S4, respectively. The current having the current value Iflows through, the constant current source circuit B1D. The capacitorsC1D and C2D have the same capacitance value as the capacitors C1 and C2.The basic operation of the electric-charge charge/discharge unit 192 isthe same as that of the electric-charge charge/discharge unit 12 g.

The capacitor C3D is provided between the node P1 and a node P2. Thecapacitor C4D is provided between the node Q1 and a node Q2. The switchSW5D and the switch SW6D are provided in series between the node P2 andthe node Q2. The switch SW5D is turned on or off based on the outputsignal QB. The switch SW6D is turned on or off based on the outputsignal Q. A bias voltage Vbias is supplied to a node between the switchSW5D and the switch SW6D. For example, when the output signal Q is atthe H level and the output signal QB is at the L level, the switch SW5Dis turned off and the switch SW6D is turned on, so that the bias voltageVbias is supplied to the node Q2 side. On the other hand, when theoutput signal Q is at the L level and the output signal QB is at the Hlevel, the switch SW5D is turned on and the switch SW6D is turned off,so that the bias voltage Vbias is supplied to the node P2 side.

The example of FIG. 16 will be described by way of example in which thereference voltage Vref is used as the bias voltage Vbias. In this case,assume that the comparison result P3 is maintained at the L level whenthe voltage level of the node P1 is at the ground voltage level, andchanges to the H level when the voltage level of the node P1 risesslightly. In the same way, assume that the comparison result Q3 ismaintained at the L level when the voltage level of the node Q1 is atthe ground voltage level, and changes to the H level when the voltagelevel of the node Q1 rises slightly. To implement such operations, inplace of the reference voltage Vref, such a slightly lower voltage thanthe reference voltage Vref that the comparators 193 and 194 do notoutput the comparison result of the H level may be used as the biasvoltage Vbias. The configuration of a reference voltage generation unitin this case will be described with reference to FIG. 19.

FIG. 19 is a diagram showing a reference voltage generation unit 15 ifor generating the reference voltage Vref and the bias voltage Vbiashaving a voltage level slightly lower than the reference voltage Vref.As shown in FIG. 19, the reference voltage generation unit 15 i has aconstant current source circuit B3 and resistance elements R1 and R2.The constant current source circuit B3 and the resistance elements R1and R2 are provided in series between the power supply voltage terminalVDD and the ground voltage terminal GND. The reference voltagegeneration unit 15 i outputs the voltage of a node N1 between theconstant current source circuit B3 and the resistance element R1 as thereference voltage Vref, and outputs the voltage of a node between theresistance element R1 and the resistance element R2 as the bias voltageVbias.

Referring back to FIG. 16, the comparator 193 compares the referencevoltage Vref and the voltage level of the node P2, and outputs thecomparison result P3. In the example of FIG. 16, the comparator 193outputs the comparison result P3 of the H level when the voltage levelof the node P2 reaches the level of the reference voltage Vref, andoutputs the comparison result P3 of the L level when the voltage levelof the node P2 is less than the reference voltage Vref.

The comparator 194 compares the reference voltage Vref and the voltagelevel of the node Q2, and outputs the comparison result Q3. In theexample of FIG. 16, the comparator 194 outputs the comparison result Q3of the H level when the voltage level of the node Q2 reaches the levelof the reference voltage Vref, and outputs the comparison result Q3 ofthe L level when the voltage level of the node Q2 is less than thereference voltage Vref.

FIG. 18 is a timing chart showing the operation of the pulse generationcircuit 19 shown in FIG. 16. In the example of FIG. 18, at time to, theoutput signal Q is at the H level, the output signal QB is at the Llevel, the output signal QD is at the H level, and the output signal QBDis at the L level. Accordingly, the SW control circuit 195 outputs theswitching signal S2 of the H level, the switching signals S1, S3, and S4of the L level, and the control signal Vctrl of the L level. In thiscase, the switch SW1D is turned off and the switch SW2D is turned on, sothat the voltage level of the node P1 falls to the L level. On the otherhand, the switches SW3D and SW4D are turned off, so that the node Q1becomes a floating state and maintains the L level. Further, the switchSW5D is turned off, so that the node P2 becomes a floating state andmaintains the voltage level of the bias voltage Vbias (reference voltageVref in this example). On the other hand, the switch SW6D is turned on,so that the node Q2 is pre-charged to the voltage level of the biasvoltage Vbias. Accordingly, the comparators 193 and 194 output thecomparison results P3 and Q3 of the L level.

When the output signal Q falls and the output signal QB rises, the SWcontrol circuit 195 outputs the switching signal S3 of the H level, theswitching signals S1, S2, and S4 of the L level, and the control signalVctrl of the H level (time t1). Accordingly, the switch SW3D is turnedon and the switch SW4D is turned off, so that the voltage level of thenode Q1 gradually rises. On the other hand, the switches SW1D and SW2Dare turned off, so that the node P1 becomes a floating state andmaintains the L level. Further, the switch SW5D is turned on and theswitch SW6D is turned off when the output signal Q falls and the outputsignal QB rises (time t1). Accordingly, the node P2 is pre-charged tothe voltage level of the bias voltage Vbias. On the other hand, the nodeQ2 becomes a floating state and maintains the voltage level of the biasvoltage Vbias.

The voltage level of the node Q2 rises as the voltage level of the nodeQ1 rises. More specifically, the node Q2 is at a voltage level obtainedby adding a rise in the voltage level of the node Q1 to the bias voltageVbias. When the voltage level of the node Q2 rises slightly higher thanthe bias voltage Vbias (around time t1), the comparator 194 raises thecomparison result Q3 with a little delay. At this time, the comparator193 outputs the comparison result P3 of the L level. Consequently, theRS flip-flop 191 lowers the output signal QD and raises the outputsignal QBD (time t2). In other words, when the voltage level of the nodeQ2 rises slightly higher than the bias voltage Vbias (around time t1),after the lapse of the delay time Td caused by the operation delay ofthe comparator 194 and the RS flip-flop 191, the output signal QD fallsand the output signal QBD rises (time t2). Since the bias voltage Vbiasis equal to or slightly lower than the reference voltage Vref, it can beconsidered that the voltage level of the node Q2 reaches such a voltagelevel as to be able to change the comparison result Q3 to the H levelimmediately after the logic value changes of the output signals Q andQB, that is, at time t1.

When the output signal QD falls and the output signal QBD rises, the SWcontrol circuit 195 outputs the switching signal S4 of the H level, theswitching signals S1 to S3 of the L level, and the control signal Vctrlof the L level (time t2). Accordingly, the switch SW3D is turned off andthe switch SW4D is turned on, so that the voltage level of the node Q1falls to the L level. Accordingly, the voltage level of the node Q2falls to the level of the bias voltage Vbias. On the other hand, theswitches SW1D and SW2D are turned off, so that the node P1 is in thefloating state and maintains the L level. The voltage level of the nodeP2 also maintains the level of the bias voltage Vbias.

Thus, the pulse generation circuit 19 raises the control signal Vctrl insynchronization with the logic value changes of the output signals Q andQB (time t1), and lowers the control signal Vctrl after the lapse of thedelay time Td (time t2). That is, the pulse generation circuit 19outputs the control signal Vctrl having substantially the same pulsewidth as the delay time Td in synchronization with the logic valuechanges of the output signals Q and QB.

Then, when the output signal Q rises and the output signal QB falls, theSW control circuit 195 outputs the switching signal S1 of the H level,the switching signals S2 to S4 of the L level, and the control signalVctrl of the H level (time t3). Accordingly, the switch SW1D is turnedon and the switch SW2D is turned off, so that the voltage level of thenode P1 gradually rises. On the other hand, the switches SW3D and SW4Dare turned off, so that the node Q1 becomes the floating state andmaintains the L level. Further, the switch SW5D is turned off and theswitch SW6D is turned on when the output signal Q rises and the outputsignal QB falls (time t3). Accordingly, the node Q2 is pre-charged tothe voltage level of the bias voltage Vbias. On the other hand, the nodeP2 becomes the floating state and maintains the voltage level of thebias voltage Vbias.

The voltage level of the node P2 rises as the voltage level of the nodeP1 rises. More specifically, the node P2 is at a voltage level obtainedby adding a rise in the voltage level of the node P1 to the bias voltageVbias. When the voltage level of the node P2 rises slightly higher thanthe bias voltage Vbias (around time t3), the comparator 193 raises thecomparison result P3 with a little delay. At this time, the comparator194 outputs the comparison result Q3 of the L level. Consequently, theRS flip-flop 191 raises the output signal QD and lowers the outputsignal QBD (time t4). In other words, when the voltage level of the nodeP2 rises slightly higher than the bias voltage Vbias (around time t3),after the lapse of the delay time Td caused by the operation delay ofthe comparator 193 and the RS flip-flop 191, the output signal QD risesand the output signal QBD falls (time t4). Since the bias voltage Vbiasis equal to or slightly lower than the reference voltage Vref, it can beconsidered that the voltage level of the node P2 reaches such a voltagelevel as to be able to change the comparison result P3 to the H levelimmediately after the logic value changes of the output signals Q andQB, that is, at time t3.

When the output signal QD rises and the output signal QBD falls, the SWcontrol circuit 195 outputs the switching signal S2 of the H level, theswitching signals S1, S3, and S4 of the L level, and the control signalVctrl of the L level (time t4). Accordingly, the switch SW1D is turnedoff and the switch SW2D is turned on, so that the voltage level of thenode P1 falls to the L level. Accordingly, the voltage level of the nodeP2 falls to the level of the bias voltage Vbias. On the other hand, theswitches SW3D and SW4D are turned off, so that the node Q1 is in thefloating state and maintains the L level. The voltage level of the nodeQ2 also maintains the level of the bias voltage Vbias. These operationsare repeated.

Thus, the pulse generation circuit 19 raises the control signal Vctrl insynchronization with the logic value changes of the output signals Q andQB (time t3), and lowers the control signal Vctrl after the lapse of thedelay time Td (time t4). That is, the pulse generation circuit 19outputs the control signal Vctrl having substantially the same pulsewidth as the delay time Td in synchronization with the logic valuechanges of the output signals Q and QB.

Eleventh Embodiment

FIG. 20 is a diagram showing a reference voltage generation unit 15 jaccording to an eleventh embodiment of the invention. The referencevoltage generation unit 15 j shown in FIG. 20 is a modification of thereference voltage generation unit 15 i shown in FIG. 19, and generatesthe reference voltage Vref and the bias voltage Vbias having a voltagelevel slightly lower than the reference voltage Vref.

In comparison with the reference voltage generation unit 15 i, thereference voltage generation unit 15 j has a variable resistance elementR1 j in place of the resistance element R1. The variable resistanceelement R1 j has a variable resistance value according to a controlsignal Ctrl1.

The reference voltage generation unit 15 j can generate the referencevoltage Vref having a desired voltage level by adjusting the resistancevalue of the variable resistance element R1 j based on the controlsignal Ctrl1. By including the reference voltage generation unit 15 j,the oscillation circuit having the pulse generation circuit 19 shown inFIGS. 13 and 15 can freely vary the oscillation frequency of the outputsignals (oscillation signals) Q and QB.

Further, the reference voltage generation unit 15 j can freely vary thedifference between the reference voltage Vref and the bias voltage Vbiasby adjusting the resistance value of the variable resistance element R1j based on the control signal Ctrl1. By including the reference voltagegeneration unit 15 j, the oscillation circuit having the pulsegeneration circuit 19 shown in FIGS. 13 and 15 can adjust the timing ofthe logic value change of the control signal Vctrl outputted from thepulse generation circuit 19.

The control signal Ctrl1 is outputted from e.g. a register M1 j providedin the oscillation circuit or a semiconductor integrated circuitincluding the oscillation circuit. The register M1 j stores informationof a control signal (external control signal) supplied from outside, andoutputs the control signal Ctrl1 based on the stored information. Thus,in the oscillation circuit according to the invention, it is possible toexternally control the control signal Ctrl1; therefore, it is possibleto vary the oscillation frequency of the output signals (oscillationsignals) Q and QB even after production. The register M1 j may generatethe control signal Ctrl1 according to a request from a CPU in place ofthe external control signal. Further, the register M1 j may be a memoryelement such as flash memory.

Twelfth Embodiment

FIG. 21 is a diagram showing a reference voltage generation unit 15 kaccording to a twelfth embodiment of the invention. The referencevoltage generation unit 15 k shown in FIG. 21 is a modification of thereference voltage generation unit 15 i shown in FIG. 19, and generatesthe reference voltage Vref and the bias voltage Vbias having a voltagelevel slightly lower than the reference voltage Vref.

In comparison with the reference voltage generation unit 15 i, thereference voltage generation unit 15 k has a variable resistance elementR1 k in place of the resistance element R1 and has a variable resistanceelement R2 k in place of the resistance element R2. The variableresistance elements R1 k and R2 k have variable resistance valuesaccording to control signals Ctrl1 and Ctrl2 respectively. The controlsignals Ctrl1 and Ctrl2 are outputted from e.g. a register M2 k providedin the oscillation circuit or a semiconductor integrated circuitincluding the oscillation circuit.

Thereby, the reference voltage generation unit 15 k can provide the sameeffect as the reference voltage generation unit 15 j shown in FIG. 20.Further, the reference voltage generation unit 15 k can generate thebias voltage Vbias having a desired voltage level by adjusting theresistance value of the variable resistance element R2 k based on thecontrol signal Ctrl2.

Thirteenth Embodiment

FIG. 22 is a diagram showing a reference voltage generation unit 15 maccording to a thirteenth embodiment of the invention. The referencevoltage generation unit 15 m shown in FIG. 22 is a modification of thereference voltage generation unit 15 i shown in FIG. 19, and generatesthe reference voltage Vref and the bias voltage Vbias having a voltagelevel slightly lower than the reference voltage Vref.

In comparison with the reference voltage generation unit 15 i, thereference voltage generation unit 15 m has a variable resistance elementR1 m in place of the resistance element R1 and has variable resistanceelements R2 m and R3 m in place of the resistance element R2. Thevariable resistance elements R1 m, R2 m, and R3 m have variableresistance values according to control signals Ctrl1, Ctrl2, and Ctrl3respectively. The control signals Ctrl1 to Ctrl3 are outputted from e.g.a register M3 m provided in the oscillation circuit or a semiconductorintegrated circuit including the oscillation circuit. The variableresistance element R2 m has a positive temperature dependence in whichthe resistance value increases with increasing temperature. The variableresistance element R3 m has a negative temperature dependence in whichthe resistance value decreases with increasing temperature.

Thereby, the reference voltage generation unit 15 m can provide the sameeffect as the reference voltage generation unit 15 k shown in FIG. 21.Further, since the reference voltage generation unit 15 m has thevariable resistance elements R2 m and R3 m having the differenttemperature dependences, the reference voltage generation unit 15 m cancancel resistance value change caused by temperature fluctuation.Therefore, the reference voltage generation unit 15 m can generate thestable reference voltage Vref even with fluctuations in temperature.

Fourteenth Embodiment

FIG. 23 is a block diagram showing a PLL to which the oscillationcircuit according to the invention is applied. While this embodimentwill be described by way of example in which the oscillation circuit 1shown in FIG. 1 is applied to the PLL, the oscillation circuit accordingto another embodiment may be applied.

The PLL 100 shown in FIG. 23 includes the oscillation circuit 1, a phasecomparator (PFD) 101, a charge pump 102, a loop filter 103, avoltage-controlled oscillator (VCO) 104, and a frequency divider 105.The phase comparator 101 and the charge pump 102 are collectivelyreferred to as a phase difference detection unit.

The oscillation circuit 1 outputs an oscillation signal as a referenceclock signal. The phase comparator 101 detects a phase differencebetween the reference clock signal from the oscillation circuit 1 and afrequency-divided clock signal from the frequency divider 105. Thecharge pump 102 generates an output voltage according to the phasedifference detected by the phase comparator 101. The loop filter 103converts the output voltage of the charge pump 102 into a DC signal, andoutputs it as a control voltage. The voltage-controlled oscillator 104outputs a clock signal having a frequency according to the controlvoltage. The frequency divider 105 frequency-divides the clock signalfrom the voltage-controlled oscillator 104, and outputs thefrequency-divided clock signal.

Thus, the PLL to which the oscillation circuit according to theinvention is applied multiplies the reference clock signal (oscillationsignal) outputted from the oscillation circuit, and thereby can generatea faster clock signal with accuracy.

Fifteenth Embodiment

FIG. 24 is a block diagram showing a semiconductor integrated circuit(LSI) to which the oscillation circuit according to the invention isapplied. While this embodiment will be described by way of example inwhich the oscillation circuit 1 shown in FIG. 1 as a clock source 1 isapplied to the semiconductor integrated circuit, the oscillation circuitaccording to another embodiment may be applied.

The semiconductor integrated circuit 200 shown in FIG. 24 includes theclock source 1, an internal circuit 201 comprised of a logic circuit anda memory, and a power source 202. The power source 202 supplies a powersupply voltage to the clock source 1 and the internal circuit 201. Whena start signal from outside is asserted, the clock source 1 operates andoutputs a clock signal (oscillation signal) having a preset frequency.The internal circuit 201 operates in synchronization with the clocksignal supplied from the clock source 1.

Thus, the semiconductor integrated circuit 200 to which the oscillationcircuit according to the invention is applied operates insynchronization with the accurate clock signal outputted from theoscillation circuit (clock source), and therefore can implement a stableoperation. Particularly in the case where the oscillation circuit havingthe pulse generation circuit 19 shown in FIGS. 13 and 15 is applied tothe semiconductor integrated circuit 200, the semiconductor integratedcircuit 200 can quickly stabilize the clock signal, and thus can reducethe starting time.

Sixteenth Embodiment

FIG. 25 is a block diagram showing a semiconductor integrated circuit(LSI) to which the oscillation circuit according to the invention isapplied. While this embodiment will be described by way of example inwhich the oscillation circuit 1 shown in FIG. 1 as a clock source 1 isapplied to the semiconductor integrated circuit, the oscillation circuitaccording to another embodiment may be applied.

The semiconductor integrated circuit 300 shown in FIG. 25 includes theclock source 1, an internal circuit 301 comprised of a logic circuit anda memory, a power source 302, a sensor 303, a clock source 304, and astarting circuit 305. The sensor 303, the clock source 304, and thestarting circuit 305 are collectively referred to as a mode switchingunit.

The power source 302 supplies a power supply voltage to the clock source1, the clock source 304, the internal circuit 301, and the startingcircuit 305. The clock source 304 outputs a low-speed clock signal ofwhich high accuracy is not required. The sensor 303 controls theassertion state of an enable signal based on a signal supplied fromoutside. For example, when the sensor 303 is requested to operate thesemiconductor integrated circuit 300 by the signal supplied fromoutside, the sensor 303 asserts the enable signal (e.g., raises theenable signal). In synchronization with the clock signal from the clocksource 304, the starting circuit 305 captures the enable signal from thesensor 303 and outputs it as a start signal. When the start signal isasserted, the clock source 1 operates and outputs a clock signal(oscillation signal) having a preset frequency. Then, the internalcircuit 301 operates in synchronization with the clock signal suppliedfrom the clock source 1.

That is, the semiconductor integrated circuit 300 operates the internalcircuit 301 by supplying the clock signal to the internal circuit 301 ina normal operation mode, and stops the operation of the internal circuit301 by stopping the supply of the clock signal to the internal circuit301 in a stop mode. Since the semiconductor integrated circuit 300 canstop the supply of the clock signal to the internal circuit 301 in thestop mode, it is possible to reduce the power consumption.

Thus, the semiconductor integrated circuit 300 to which the oscillationcircuit according to the invention is applied operates insynchronization with the accurate clock signal outputted from theoscillation circuit (clock source), and therefore can implement a stableoperation. Particularly in the case where the oscillation circuit havingthe pulse generation circuit 19 shown in FIGS. 13 and 15 is applied tothe semiconductor integrated circuit 300, the semiconductor integratedcircuit 200 can quickly stabilize the clock signal, and thus can reducethe starting time of each switching from the stop mode to the normaloperation mode to achieve more effective operation.

Layout Configuration Example of Oscillation Circuit According to theInvention

Hereinafter, the layout configuration of the oscillation circuitaccording to the invention will be described. FIG. 26 is a diagramshowing an example of the layout configuration of the oscillationcircuit according to the invention. In FIG. 26, an example of the layoutconfiguration of the oscillation circuit 1 in FIG. 1 is representativelyshown.

As shown in FIG. 26, the RS flip-flop 11, the pair of comparators 13 and14 disposed side-by-side in the horizontal direction of the figure, andthe pair of capacitors C1 and C2 disposed side-by-side in the horizontaldirection of the figure are closely disposed in sequence from the top tothe bottom of the figure. Further, the RS flip-flop 11, the comparators13 and 14, and the capacitors C1 and C2 are disposed symmetrically withthe vertical direction of the figure as a symmetry axis. Thus, a circuitfor generating one (output signal Q) of the pair of differential signalsand a circuit for generating the other (output signal QB) of the pair ofdifferential signals are disposed symmetrically, which reduces thevariation in accuracy between the differential signals.

Further, on the comparator 13, four gate electrodes are equally spacedin sequence from the middle to the bottom of the comparator 13. Thelongitudinal direction of the gate electrodes is the horizontaldirection of the figure. In the example of FIG. 26, the top two of thefour gate electrodes are used as the inverting input terminal of thecomparator 13, and the bottom two electrodes are used as thenon-inverting input terminal of the comparator 13. The two gateelectrodes for the inverting input terminal of the comparator 13 and thetwo gate electrodes for the non-inverting input terminal are disposedsymmetrically with the horizontal direction of the figure as a symmetryaxis. The layout configuration of four gate electrodes on the comparator14 is the same as that of the comparator 13, and will not be describedagain.

This layout configuration can reduce the length of wiring for couplingthe comparator 13 and the capacitor C1 and the length of wiring forcoupling the comparator 14 and the capacitor C2, which suppressesmalfunctions due to the influence of wiring capacitance.

FIG. 27 is a diagram showing an example of the layout configuration ofthe oscillation circuit according to the invention. In FIG. 27, anexample of the layout configuration of the oscillation circuit 1 in FIG.1 is representatively shown. Hereinafter, only different portions fromthe layout configuration of FIG. 26 will be described.

As shown in FIG. 27, on the comparator 13, four gate electrodes areequally spaced in sequence from right to left in the lower part of thecomparator 13. The longitudinal direction of the gate electrodes is thevertical direction of the figure. In the example of FIG. 27, the righttwo of the four gate electrodes are used as the inverting input terminalof the comparator 13, and the left two electrodes are used as thenon-inverting input terminal of the comparator 13. The two gateelectrodes for the inverting input terminal of the comparator 13 and thetwo gate electrodes for the non-inverting input terminal are disposedsymmetrically with the vertical direction of the figure as a symmetryaxis. The layout configuration of four gate electrodes on the comparator14 is the same as that of the comparator 13, and will not be describedagain.

This layout configuration can provide the same effect as the layoutconfiguration shown in FIG. 26.

FIG. 28 is a diagram showing an example of the layout configuration ofthe oscillation circuit having the pulse generation circuit 19 shown inFIGS. 13 and 15. As shown in FIG. 28, the pair of capacitors C1D andC2D, the pair of capacitors C3D and C4D, the pair of comparators 193 and194, the pair of comparators 13 and 14, and the pair of capacitors C1and C2 are each disposed side-by-side in the horizontal direction of thefigure. These pairs are closely disposed in sequence from the top to thebottom of the figure. Further, the pair of capacitors C1D and C2D, thepair of capacitors C3D and C4D, the pair of comparators 193 and 194, theRS flip-flop 191, the RS flip-flop 11, the pair of comparators 13 and14, and the pair of capacitors C1 and C2 are disposed symmetrically withthe vertical direction of the figure as a symmetry axis. Thus, circuitsfor generating ones (output signals Q, QD) of the pairs of differentialsignals and circuits for generating the others (output signal QB, QBD)of the pairs of differential signals are disposed symmetrically, whichreduces the variation in accuracy between the differential signals.

Further, on the comparator 193, four gate electrodes are equally spacedin sequence from right to left in the upper part of the comparator 193.The longitudinal direction of the gate electrodes is the verticaldirection of the figure. In the example of FIG. 28, the right two of thefour gate electrodes are used as the inverting input terminal of thecomparator 193, and the left two electrodes are used as thenon-inverting input terminal of the comparator 193. The two gateelectrodes for the inverting input terminal of the comparator 193 andthe two gate electrodes for the non-inverting input terminal aredisposed symmetrically with the vertical direction of the figure as asymmetry axis. The layout configuration of four gate electrodes on thecomparator 194 is the same as that of the comparator 193, and will notbe described again. Further, the layout configuration of the respectivefour gate electrodes disposed on the comparators 13 and 14 is the sameas that shown in FIG. 27, and will not be described again.

This layout configuration can reduce the length of wiring for couplingthe comparator 13 and the capacitor C1, the length of wiring forcoupling the comparator 14 and the capacitor C2, the length of wiringfor coupling the comparator 193 and the capacitor C3D, and the length ofwiring for coupling the comparator 194 and the capacitor C4D, whichsuppresses malfunctions due to the influence of wiring capacitance.

Layout Configuration Example of Capacitor

Next, the layout configuration of the capacitor used in the oscillationcircuit according to the invention will be described. FIG. 29Arepresentatively shows an example of the layout configuration of thecapacitor C1. Further, FIG. 29B representatively shows another exampleof the layout configuration of the capacitor C1.

As shown in FIG. 29A, one electrode of the capacitor C1 is formed by awiring disposed in the upper part of two laminated wiring layers, andthe other electrode of the capacitor C1 is formed by a wiring disposedin the lower part of the two laminated wiring layers. Thus, thecapacitor C1 is configured by the respective wirings disposed in the twolaminated wiring layers, which suppresses capacitance value change dueto fluctuations in temperature or power supply voltage.

As shown in FIG. 29B, one electrode of the capacitor C1 is formed by afirst wiring having a plurality of comb-like protrusions disposed in awiring layer. Further, the other electrode of the capacitor C1 is formedby a second wiring having a plurality of comb-like protrusions disposedin the same wiring layer as the first wiring. The first wiring and thesecond wiring are opposed in the horizontal direction of the figure, andthe protrusions are alternately arranged. Thus, the capacitor C1 isconfigured by the two wirings disposed in the same wiring layer, whichsuppresses capacitance value change due to fluctuations in temperatureor power supply voltage.

As described above, the oscillation circuits according to the first tosixteenth embodiments can accurately output the oscillation signalshaving the desired frequency even when the delay time Td caused by theoperation delay of the comparator and the RS flip-flop varies withfluctuations in temperature or power supply voltage.

The present invention is not limited to the above embodiments, and canbe modified as appropriate without departing from the spirit and scopeof the invention. While the above embodiments have been described by wayof example in which the capacitors C1 and C2 have substantially the samecapacitance value, the invention is not limited thereto. The respectivecapacitance values of the capacitors C1 and C2 can be changed asappropriate in accordance with the duty ratio between the output signals(oscillation signals) Q and QB.

Further, while the above embodiments have been described by way ofexample in which the current source circuit (e.g., constant currentsource circuit B1 in FIG. 1) is provided on either the power supplyvoltage terminal VDD side or the ground voltage terminal GND side andthe capacitors C1 and C2 are provided at the nodes X1 and Y1respectively in the electric-charge charge/discharge unit, the inventionis not limited thereto. The electric-charge charge/discharge unit can bemodified as appropriate to a circuit configuration in which respectivecurrent source circuits are individually provided on the power supplyvoltage terminal VDD side and the ground voltage terminal GND side andone common capacitor is provided at a common node in place of the nodesX1 and Y1. In this case, the common node is coupled to, for example, thenon-inverting input terminal of the comparator 13 and the invertinginput terminal of the comparator 14. Further, a reference voltage A issupplied to the inverting input terminal of the comparator 13, and areference voltage B different from the reference voltage A is suppliedto the non-inverting input terminal of the comparator 14. That is, inthis case, the comparator 13 detects whether or not the voltage level ofthe common node which gradually rises by current flowing through thecurrent source circuit on the power supply voltage terminal VDD side hasreached the reference voltage A. On the other hand, the comparator 14detects whether or not the voltage level of the common node whichgradually falls by current flowing through the current source circuit onthe ground voltage terminal GND side has reached the reference voltageB.

Further, while the above embodiments have been described by way ofexample in which the one current source circuit (e.g., constant currentsource circuit B1 in FIG. 1) for feeding the current to the nodes X1 andY1 is provided in the electric-charge charge/discharge unit, theinvention is not limited thereto. The electric-charge charge/dischargeunit can be modified as appropriate to a circuit configuration in whicha current source circuit for feeding current to the node X1 and acurrent source circuit for feeding current to the node Y1 are providedindividually.

Moreover, the oscillation circuit disclosed in Patent Document 2 isconfigured without a comparator having a response delay time, and it isnot considered possible to easily think of the application of thetechnique as it is to the oscillation circuit having comparatorsdisclosed in Patent Document 1.

What is claimed is:
 1. An oscillation circuit comprising: a latch for generating an output signal based on a first signal and a second signal; an electric-charge charge/discharge unit which has first and second capacitors, and charges or discharges the first and second capacitors complementarily based on the output signal; a first comparator which compares a first voltage according to electric charge accumulated in the first capacitor and a first reference voltage, and outputs the first signal; a second comparator which compares a second voltage according to electric charge accumulated in the second capacitor and the first reference voltage, and outputs the second signal; and a control unit for controlling a timing, to compensate for variations of signals in the latch, the first comparator, and the second comparator, at which respective voltage levels of the first reference voltage and the first voltage match, wherein the control unit controls the voltage level of the first reference voltage in accordance with the frequency of the output signal.
 2. The oscillation circuit according to claim 1, wherein the control unit further comprises a control voltage generation unit which generates a control voltage having a voltage level according to the frequency of the output signal of the latch.
 3. The oscillation circuit according to claim 2, wherein the control voltage generation unit further includes a constant current source and a plurality of switches which generates the control voltage having the voltage level according to the frequency of the output signal of the latch.
 4. The oscillation circuit according to claim 3, wherein the control unit further comprises an comparison voltage generation unit that includes an operational amplifier connected with a resistance element and a third capacitor to generate a comparison voltage according to a different between an average value of the control voltage from the control voltage generation unit and the first reference voltage.
 5. The oscillation circuit according to claim 1, wherein the first signal comprises a set signal and a second signal comprises a reset signal.
 6. The oscillation circuit according to claim 1, wherein the control unit increases the voltage level of the first reference voltage with an increase in the frequency of the output signal, and decreases the voltage level of the first reference voltage with a decrease in the frequency of the output signal.
 7. The oscillation circuit according to claim 1, wherein the control unit controls slew rates of the first and second voltages in accordance with the frequency of the output signal.
 8. The oscillation circuit according to claim 1, wherein the control unit controls the timing, to compensate for variations of signals in the latch, the first comparator, and the second comparator, at which respective voltage levels of the first reference voltage and the first voltage match and a timing, to compensate for variations of signals in the latch, the first comparator, and the second comparator, at which respective voltage levels of the first reference voltage and the second voltage match in response to a frequency of the output signal.
 9. The oscillation circuit according to claim 1, wherein the latch comprises an RS flip-flop.
 10. The oscillation circuit according to claim 1, wherein the control unit comprises: a control voltage generation unit for generating a control voltage according to the frequency of the output signal; and a voltage control unit for generating a comparison voltage according to a difference between a second reference voltage and the control voltage, as the first reference voltage.
 11. The oscillation circuit according to claim 10, wherein the control voltage generation unit includes a first constant current source circuit for feeding a constant current and a switched capacitor resistor having a resistance value according to the frequency of the output signal, and generates the control voltage having a voltage level determined based on a current value of the current flowing through the first constant current source circuit and the resistance value of the switched capacitor resistor.
 12. An oscillation circuit comprising: a latch for generating an output signal based on a first signal and a second signal; an electric-charge charge/discharge unit which has first and second capacitors, and charges or discharges the first and second capacitors complementarily based on the output signal; a first comparator which compares a first voltage according to electric charge accumulated in the first capacitor and a first reference voltage, and outputs the first signal; a second comparator which compares a second voltage according to electric charge accumulated in the second capacitor and the first reference voltage, and outputs the second signal; and a control unit for controlling a timing at which respective voltage levels of the first reference voltage and the first voltage match and a timing at which respective voltage levels of the first reference voltage and the second voltage match in accordance with a frequency of the output signal, wherein the control unit includes a control voltage generation unit for generating a control voltage according to the frequency of the output signal and a voltage control unit for generating a comparison voltage according to a difference between a second reference voltage and the control voltage, as the first reference voltage.
 13. The oscillation circuit according to claim 12, wherein the electric-charge charge/discharge unit further comprises a second constant current source circuit for feeding a constant current and a switch unit for controlling continuity between the second constant current source circuit and the first capacitor, continuity between the second constant current source circuit and the second capacitor, continuity between a first power source and the first capacitor, and continuity between the first power source and the second capacitor, based on the output signal.
 14. The oscillation circuit according to claim 12, wherein the electric-charge charge/discharge unit further generates the control voltage having a voltage level determined based on a current value of the current flowing through the second constant current source circuit and a resistance value of a switched capacitor resistor comprised of the switch unit and the first and second capacitors.
 15. The oscillation circuit according to claim 12, wherein the voltages to the first and second capacitors are supplied to inverting input terminals of the first and second comparators respectively, and a comparison voltage is supplied to non-inverting input terminals of the first and second comparators.
 16. An oscillation circuit comprising: a latch for generating an output signal based on a first signal and a second signal; an electric-charge charge/discharge unit which includes first and second capacitors, and charges or discharges the first and second capacitors complementarily based on the output signal, the electric-charge/discharge unit generates a control voltage according to the frequency of the output signal; a first comparator which compares a first voltage according to electric charge accumulated in the first capacitor and a first reference voltage, and outputs the first signal; a second comparator which compares a second voltage according to electric charge accumulated in the second capacitor and the first reference voltage, and outputs the second signal; and a control unit for controlling a timing at which respective voltage levels of the first reference voltage and the first voltage match and a timing at which respective voltage levels of the first reference voltage and the second voltage match in accordance with a frequency of the output signal.
 17. The oscillation circuit according to claim 16, wherein the control unit includes a control voltage generation unit for generating a control voltage according to the frequency of the output signal and a voltage control unit for controlling slew rates of the first and second voltages in accordance with a difference between a second reference voltage as the first reference voltage and the control voltage.
 18. The oscillation circuit according to claim 16, wherein the control voltage generation unit includes a first constant current source circuit for feeding a constant current and a switched capacitor resistor having a resistance value according to the frequency of the output signal, and generates the control voltage having a voltage level determined based on a current value of the current flowing through the first constant current source circuit and the resistance value of the switched capacitor resistor.
 19. The oscillation circuit according to claim 16, wherein the voltage control unit generates a comparison voltage according to a difference between the second reference voltage and the control voltage, wherein the electric-charge charge/discharge unit further includes a variable current source circuit for feeding a current according to the comparison voltage and a switch unit for controlling continuity between the variable current source circuit and the first capacitor, controlling continuity between the variable current source circuit and the second capacitor, continuity between a first power source and the first capacitor, and continuity between the first power source and the second capacitor, based on the output signal, and wherein the first and second capacitors comprise variable capacitors having capacitance values according to the comparison voltage.
 20. A PLL (Phase-locked loop) comprising: the oscillation circuit according to claim
 16. 